Remove unnecessary getTarget call now that the subtarget is cached
on the machine function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217070 91177308-0d34-0410-b5e6-96231b3b80d8
Remove resetSubtargetFeatures as it is unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217071 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Add an SSE4.1 mode to this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217072 91177308-0d34-0410-b5e6-96231b3b80d8
[JIT] Add an out-of-line definition for the virtual destructor in
JITEventListener. This used to be in the old JIT (last line of the file)
and everyone just "happened" to pick it up from there. =/ Doh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217073 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel] Rename public visible FastISel functions. NFC.

This commit renames the following public FastISel functions:
LowerArguments -> lowerArguments
SelectInstruction -> selectInstruction
TargetSelectInstruction -> fastSelectInstruction
FastLowerArguments -> fastLowerArguments
FastLowerCall -> fastLowerCall
FastLowerIntrinsicCall -> fastLowerIntrinsicCall
FastEmitZExtFromI1 -> fastEmitZExtFromI1
FastEmitBranch -> fastEmitBranch
UpdateValueMap -> updateValueMap
TargetMaterializeConstant -> fastMaterializeConstant
TargetMaterializeAlloca -> fastMaterializeAlloca
TargetMaterializeFloatZero -> fastMaterializeFloatZero
LowerCallTo -> lowerCallTo

Reviewed by Eric

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217074 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.

This is the final round of renaming. This changes tblgen to emit lower-case
function names for FastEmitInst_* and FastEmit_*, and updates all its uses
in the source code.

Reviewed by Eric

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217075 91177308-0d34-0410-b5e6-96231b3b80d8
Use target-dependent emitLeading/TrailingFence instead of the target-independent insertLeading/TrailingFence (in AtomicExpandPass)

Fixes two latent bugs:
- There was no fence inserted before expanded seq_cst load (unsound on Power)
- There was only a fence release before seq_cst stores (again unsound, in particular on Power)
    It is not even clear if this is correct on ARM swift processors (where release fences are
    DMB ishst instead of DMB ish). This behaviour is currently preserved on ARM Swift
    as it is not clear whether it is incorrect. I would love to get documentation stating
    whether it is correct or not.
These two bugs were not triggered because Power is not (yet) using this pass, and these
behaviours happen to be (mostly?) working on ARM
(although they completely butchered the semantics of the llvm IR).

See:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075821.html
for an example of the problems that can be caused by the second of these bugs.

I couldn't see a way of fixing these in a completely target-independent way without
adding lots of unnecessary fences on ARM, hence the target-dependent parts of this
patch.

This patch implements the new target-dependent parts only for ARM (the default
of not doing anything is enough for AArch64), other architectures will use this
infrastructure in later patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217076 91177308-0d34-0410-b5e6-96231b3b80d8
Make some helpers static or move into the llvm namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217077 91177308-0d34-0410-b5e6-96231b3b80d8