PR c++/63139
	* pt.c (tsubst_pack_expansion): Simplify substitution into T....
	(tsubst): Don't throw away PACK_EXPANSION_EXTRA_ARGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215171 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}

gcc/

	* config/aarch64/arm_neon.h (vmull_high_lane_s16): Fix argument
	types.
	(vmull_high_lane_s32): Likewise.
	(vmull_high_lane_u16): Likewise.
	(vmull_high_lane_u32): Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215176 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64 Testsuite] Add execution test of vset(q?)_lane intrinsics.

	* gcc.target/aarch64/vset_lane_1.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215177 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Replace temporary inline assembler for vset_lane

	* config/aarch64/arm_neon.h (aarch64_vset_lane_any): New (*2).
	(vset_lane_f32, vset_lane_f64, vset_lane_p8, vset_lane_p16,
	vset_lane_s8, vset_lane_s16, vset_lane_s32, vset_lane_s64,
	vset_lane_u8, vset_lane_u16, vset_lane_u32, vset_lane_u64,
	vsetq_lane_f32, vsetq_lane_f64, vsetq_lane_p8, vsetq_lane_p16,
	vsetq_lane_s8, vsetq_lane_s16, vsetq_lane_s32, vsetq_lane_s64,
	vsetq_lane_u8, vsetq_lane_u16, vsetq_lane_u32, vsetq_lane_u64):
	Replace inline assembler with __aarch64_vset_lane_any.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215179 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Simplify vreinterpret for float64x1_t using casts.

	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers,
	TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP,
	aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US,
	aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD):
	Delete.

	(aarch64_fold_builtin): Remove all reinterpret cases.

	* config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete.

	* config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete.

	* config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>,
	aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>,
	aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>,
	aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>,
	aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>,
	aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>,
	aarch64_reinterpretv2df<mode>): Delete.

	* config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete.

	* config/aarch64/arm_neon.h (vreinterpret_p8_f64,
	vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32,
	vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8,
	vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8,
	vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64,
	vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64,
	vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64,
	vreinterpret_u32_f64): Use cast.

	* config/aarch64/iterators.md (VD_RE): Delete.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215180 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* doc/invoke.texi ([-Wmissing-field-initializers]): Update.

/cp
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* typeck2.c (process_init_constructor_record): Do not warn about
	missing field initializer if EMPTY_CONSTRUCTOR_P (init).

/testsuite
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* g++.dg/warn/Wmissing-field-initializers-1.C: New.
	* g++.old-deja/g++.other/warn5.C: Adjust.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215186 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/htm.md (tabort, tabortdc, tabortdci, tabortwc,
	tabortwci, tbegin, tcheck, tend, trechkpt, treclaim, tsr): Use xor
	instead of minus.
	* config/rs6000/vector.md (cr6_test_for_zero_reverse,
	cr6_test_for_lt_reverse): Ditto.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215187 138bc75d-0d04-0410-961f-82ee72b054a4
Introduce LABEL_REF_LABEL

gcc/ChangeLog:
2014-09-11  David Malcolm  <dmalcolm@redhat.com>

	* rtl.h (LABEL_REF_LABEL): New macro.

	* alias.c (rtx_equal_for_memref_p): Use LABEL_REF_LABEL in place
	of XEXP (, 0), where we know that we have a LABEL_REF.
	* cfgbuild.c (make_edges): Likewise.
	(purge_dead_tablejump_edges): Likewise.
	* cfgexpand.c (convert_debug_memory_address): Likewise.
	* cfgrtl.c (patch_jump_insn): Likewise.
	* combine.c (distribute_notes): Likewise.
	* cse.c (hash_rtx_cb): Likewise.
	(exp_equiv_p): Likewise.
	(fold_rtx): Likewise.
	(check_for_label_ref): Likewise.
	* cselib.c (rtx_equal_for_cselib_1): Likewise.
	(cselib_hash_rtx): Likewise.
	* emit-rtl.c (mark_label_nuses): Likewise.
	* explow.c (convert_memory_address_addr_space): Likewise.
	* final.c (output_asm_label): Likewise.
	(output_addr_const): Likewise.
	* gcse.c (add_label_notes): Likewise.
	* genconfig.c (walk_insn_part): Likewise.
	* genrecog.c (validate_pattern): Likewise.
	* ifcvt.c (cond_exec_get_condition): Likewise.
	(noce_emit_store_flag): Likewise.
	(noce_get_alt_condition): Likewise.
	(noce_get_condition): Likewise.
	* jump.c (maybe_propagate_label_ref): Likewise.
	(mark_jump_label_1): Likewise.
	(redirect_exp_1): Likewise.
	(rtx_renumbered_equal_p): Likewise.
	* lra-constraints.c (operands_match_p): Likewise.
	* reload.c (operands_match_p): Likewise.
	(find_reloads): Likewise.
	* reload1.c (set_label_offsets): Likewise.
	* reorg.c (get_branch_condition): Likewise.
	* rtl.c (rtx_equal_p_cb): Likewise.
	(rtx_equal_p): Likewise.
	* rtlanal.c (reg_mentioned_p): Likewise.
	(rtx_referenced_p): Likewise.
	(get_condition): Likewise.
	* sched-vis.c (print_value): Likewise.
	* varasm.c (const_hash_1): Likewise.
	(compare_constant): Likewise.
	(const_rtx_hash_1): Likewise.
	(output_constant_pool_1): Likewise.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215190 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-11  Marc Glisse  <marc.glisse@inria.fr>

	PR target/58757
gcc/c-family/
	* c-cppbuiltin.c (builtin_define_float_constants): Correct
	__*_DENORM_MIN__ without denormals.
gcc/
	* ginclude/float.h (FLT_TRUE_MIN, DBL_TRUE_MIN, LDBL_TRUE_MIN):
	Directly forward to __*_DENORM_MIN__.
gcc/testsuite/
	* gcc.dg/c11-true_min-1.c: New testcase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215191 138bc75d-0d04-0410-961f-82ee72b054a4
2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (rs6000_mftb_<mode>): Use mode iterator
	GPR instead of P.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215193 138bc75d-0d04-0410-961f-82ee72b054a4
Also turn off OPTION_MASK_ABI_X32 for -m16

	PR target/63228
	* config/i386/i386.c (ix86_option_override_internal): Also turn
	off OPTION_MASK_ABI_X32 for -m16.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215194 138bc75d-0d04-0410-961f-82ee72b054a4
	* common.opt (flto-odr-type-merging): New flag.
	* ipa-deivrt.c (hash_type_name): Use ODR names for hasing if availale.
	(types_same_for_odr): Likewise.
	(odr_subtypes_equivalent_p): Likewise.
	(add_type_duplicate): Do not walk type variants.
	(register_odr_type): New function.
	* ipa-utils.h (register_odr_type): Declare.
	(odr_type_p): New function.
	* langhooks.c (lhd_set_decl_assembler_name): Do not compute
	TYPE_DECLs
	* doc/invoke.texi (-flto-odr-type-merging): Document.
	* tree.c (need_assembler_name_p): Compute ODR names when asked
	for it.
	* tree.h (DECL_ASSEMBLER_NAME): Update comment.

	* lto.c (lto_read_decls): Register ODR types.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215196 138bc75d-0d04-0410-961f-82ee72b054a4
Daily bump.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215199 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/
	* ira.h (ira_finish_once): Delete.
	* ira-int.h (target_ira_int::~target_ira_int): Declare.
	(target_ira_int::free_ira_costs): Likewise.
	(target_ira_int::free_register_move_costs): Likewise.
	(ira_finish_costs_once): Delete.
	* ira.c (free_register_move_costs): Replace with...
	(target_ira_int::free_register_move_costs): ...this new function.
	(target_ira_int::~target_ira_int): Define.
	(ira_init): Call free_register_move_costs as a member function rather
	than a global function.
	(ira_finish_once): Delete.
	* ira-costs.c (free_ira_costs): Replace with...
	(target_ira_int::free_ira_costs): ...this new function.
	(ira_init_costs): Call free_ira_costs as a member function rather
	than a global function.
	(ira_finish_costs_once): Delete.
	* target-globals.c (target_globals::~target_globals): Call the
	target_ira_int destructor.
	* toplev.c: Include lra.h.
	(finalize): Call lra_finish_once rather than ira_finish_once.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215200 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512. Extend gather insn patterns.

gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_gathersi<mode>"): Rename from
	"avx512f_gathersi<mode>".
	(define_insn "*avx512f_gathersi<mode>"): Use VI48F.
	(define_insn "*avx512f_gathersi<mode>_2"): Ditto.
	(define_expand "<avx512>_gatherdi<mode>"): Rename from
	"avx512f_gatherdi<mode>".
	(define_insn "*avx512f_gatherdi<mode>"): Use VI48F.
	(define_insn "*avx512f_gatherdi<mode>_2"): Use VI48F, add 128/256-bit
	wide versions.
	(define_expand "<avx512>_scattersi<mode>"): Rename from
	"avx512f_scattersi<mode>".
	(define_insn "*avx512f_scattersi<mode>"): Use VI48F.
	(define_expand "<avx512>_scatterdi<mode>"): Rename from
	"avx512f_scatterdi<mode>".
	(define_insn "*avx512f_scatterdi<mode>"): Use VI48F.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215201 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512.  Extend max/min insn patterns.

gcc/
	* config/i386/sse.md (VI128_256): Delete.
	(define_mode_iterator VI124_256): New.
	(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
	(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
	(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
	(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
	"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
	(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
	(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
	iterator.
	(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
	in presence of AVX-512.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215202 138bc75d-0d04-0410-961f-82ee72b054a4
AVX-512. Extend vpternlog, valign, vrotate insns.

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI48_AVX512VL): New.
	(define_expand "<avx512>_vternlog<mode>_maskz"): Rename from
	"avx512f_vternlog<mode>_maskz" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode><sd_maskz_name>"): Rename
	from "avx512f_vternlog<mode><sd_maskz_name>" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode>_mask"): Rename from
	"avx512f_vternlog<mode>_mask" and update mode iterator.
	(define_insn "<mask_codefor><avx512>_align<mode><mask_name>"): Rename
	from "<mask_codefor>avx512f_align<mode><mask_name>" and update mode
	iterator.
	(define_insn "<avx512>_<rotate>v<mode><mask_name>"): Rename from
	"avx512f_<rotate>v<mode><mask_name>" and update mode iterator.
	(define_insn "<avx512>_<rotate><mode><mask_name>"): Rename from
	"avx512f_<rotate><mode><mask_name>" and update mode iterator.
	(define_insn "clz<mode>2<mask_name>"): Use VI48_AVX512VL mode iterator.
	(define_insn "<mask_codefor>conflict<mode><mask_name>"): Ditto.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215203 138bc75d-0d04-0410-961f-82ee72b054a4
[Ree] Ensure inserted copy don't change the number of hard registers

2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>

  gcc/
    * ree.c (combine_reaching_defs): Ensure inserted copy don't change the
    number of hard registers.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215205 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost handling
  of CALLER_SAVE_REGS and POINTER_REGS.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215206 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Fix cost for Q register moves

2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
  move handling.
  (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
  now handled correctly.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215207 138bc75d-0d04-0410-961f-82ee72b054a4