Fixed a type in $mem model in simlib.v
More changes to simlib to make it friendlier to a wider range of tools
Fixed parsing of verilog macros at end of line
Fixed $lut simlib model for a wider range of tools
Added Verilog parser support for asserts
Added $assert cell
Added $assert support to satgen
Added sat -tempinduc and sat -prove-asserts
Added hilomap command
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
assert feature