acpi: add DMAR table to ACPI tables

If object of TYPE_INTEL_IOMMU_DEVICE exists, add DMAR table to ACPI RSDT
table. For now the DMAR table indicates that there is only one hardware
unit without INTR_REMAP capability on the platform.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: check definitions of CSRs and change the capability registers

Check and correct the definitions of all the CSRs in intel_iommu.c, including
the default values, bit semantics and so on.
Change the value of the Capability Register and Extended Capability Register
to make only the simplest functionality remain.
Add function define_quad_wo() for defining the write-only property of 64-bit.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: fixup coding style

Fixup coding style issue in hw/i386/intel_iommu.c and
include/hw/i386/intel_iommu.h.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: add basic responses to CSRs accesses

Add basic responses to some basic CSRs accesses. Logics are not intact yet.
Now Linux seems to be able to initialize the VT-d

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: modify the mechanism to response to basic CSRs accesses

Change the mechanism to response to basic CSRs accesses. Add XXX_REG_HI for
64-bit register XXX_REG, to identify the high half 32-bit of the register.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: add Second Level Page Table walking functions

Add some helper functions for SLPT walk. Check if the mapping is
1 to 1.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
q35: add IOMMU address space support

Add basic framework for IOMMU translation. q35 uses pci_setup_iommu() to
register a AddressSpace for IOMMU. Right now q35 uses one AddressSpace for
all buses/devices, this should be fixed later.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: some trivial fixups

Use PRIx64 for printing uint64_t. Some small fixups.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: change endianness of vtd_mem_ops to DEVICE_LITTLE_ENDIAN

Change the endianness of vtd_mem_ops from DEVICE_NATIVE_ENDIAN to
DEVICE_LITTLE_ENDIAN.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
pci: assign devfn to pci_dev before calling pci_device_iommu_address_space()

In function do_pci_register_device() in file hw/pci/pci.c, move the assignment
of pci_dev->devfn to the position before the call to
pci_device_iommu_address_space(pci_dev) which will use the value of
pci_dev->devfn.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: fix q35 IOMMU address space support

Now each bus/device in q35 will have it's own address space, which is achieved
by:
1. Adding struct vtd_address_space containing AddressSpace, MemoryRegion and
its corresponding bus number and devfn;
2. Instead of having single AddressSpace and MemoryRegion, struct
intel_iommu_state now maintains an array of pointers to vtd_address_space,
indexed by bus number and devfn;
3. Given bus number and devfn, q35_host_dma_iommu() will look up the array
of vtd_address_space in intel_iommu_state to find out corresponding
AddressSpace, do necessary initialization, then return this AddressSpace;
4. All the MemoryRegionIOMMUOps are the same one, maintained by the field
iommu_ops of intel_iommu_state;
5. All dma accesses will call vtd_iommu_translate() to do the translation and
now it can know the device info of this access;
6. Each bus should call pci_setup_iommu().

Bugs:
1. The address to be translated does not have a corresponding present entry in
Second Level Page Table.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
ahci: map memory via device's address space instead of address_space_memory

In map_page() in hw/ide/ahci.c, replace cpu_physical_memory_map() and
cpu_physical_memory_unmap() with dma_memory_map() and dma_memory_unmap(),
because ahci devices should not access memory directly but via their address
space. Add an AddressSpace parameter to map_page(). In order to call
map_page(), we should pass the AHCIState.as as the AddressSpace argument.
After fixing this, the guest Linux can boot normally with intel iommu on.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
q35: remove duplicate initialization when initializing vtd

In mch_init_dmar(), remove the call to object_initialize() because
the initialization is done in object_new().

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: change the way to maintain the array of address spaces in intel_iommu_state

Now intel_iommu_state.address_spaces is an array indexed by bus number, whose
elements each points to a table (initialized when needed). The table contains
pointers to vtd_address_space (initialized when needed), indexed by devfn.
This is an optimized method than before in saving memory space.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: small fixup with typedef

Separate typedef from struct definitions for vtd_address_space and
intel_iommu_state since it may cause errors with older compilers.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: rename intel_iommu_state to IntelIOMMUState

Rename struct intel_iommu_state to IntelIOMMUState.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: rename vtd_address_space to VTDAddressSpace

Rename struct vtd_address_space to VTDAddressSpace.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: comment out some prints to eliminate unnecessary noises

Comment out some prints to eliminate unnecessary noises. They may be useful
for debug sometimes. However, too many noises can slow down QEMU.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: support 64K domains with 16-bit id

Change the definition of the number of domains supported. Now the Capability
Register reports that 16-bit domain id is supported.
VTD_DOMAIN_ID_SHIFT should be used to check context-entry which has not been
done yet.

Signed-off-by: Le Tan <tamlokveer@gmail.com>
intel-iommu: clear up the dfinitions of MGAW and SAGAW in Capability Register

Add some macros for the definitions of MGAW and SAGAW in Capability Register
instead of instant number. These two fields may be used in translation.

Signed-off-by: Le Tan <tamlokveer@gmail.com>