fixup: gpio-tegra.h (board-grouper-power.c)
arm: tegra grouper:fix screen flicker when kernel boot up.

set vdd_pnl as 'boot_on' to avoid dropping panel VDD.
arm: tegra: grouper: change SD1 power up period

To reduce delay between CORE_PWR_REQ and VDD_CORE, changed SD1 power up
period from 1 to 0.
ARM: tegra: cleanup wake header usage

Removed unused wake header file from Tegra board files
ARM: tegra: name the supply name of regulator rails

Provide the name of the regulator rails of MAX77663 from
platform data in place of relying on the name given by
driver.
mfd: max77663: register rtc sub driver as mfd sub device

Register RTC sub driver for PMIC MAX77663 as mfd sub device rather
than registering from board file.
regulator: max77663: register all regulators in single probe

Register the max77663 regulator sub driver as regulator-pmic and
register all regulators in single probe calls.
This will ease the DT porting.
arm: tegra: fix power down sequence fps/ame

Fix power down sequence to align with POR. FPS, GPIO and
AME part.

LDO4 tracking is not disabled.

Affcted regs:

FPS_SD3
FPS_SD2
FPS_SD1
FPS_L4
FPS_L3
AME_GPIO
GPIO3
GPIO4
CNFG1_L4
CNFG1SD0
CNFG1SD1
regulator: max77663: remove non-required platform data

Some of platform data line init_apply, init_voltage,
init_state is nto require as the same functionality
can be found through the regulator init data.
Hence removing this paramter to configure through
platform data.
arm: tegra: Board files settings for LP1 0.95V CoreV

Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.
arm: tegra: usb_phy: enable pllu_regulator

Change to enable the pllu regulator.
ARM: tegra: power: Add LP1 cold low voltage parameter

Currently, if CONFIG_TEGRA_LP1_LOW_COREVOLTAGE is enabled,
we decrease core voltage to a level specified via lp1_core_volt_low
in each platform's board file.

Add another level, lp1_core_volt_low_cold, which will be used if
there's a low temperature core voltage floor set during LP1 entry.
Only one voltage floor exists for T30 and T114, so only one additional
low voltage entry has been added.
arm: tegra: grouper: bring power up-to-date with kai

This fixes all build errors for board-grouper-power.c