AND gate code generation test
codegen tests for OR and NOT
variable name fixes
test refactor: add schematicToVHDL() helper
test refactoring: findBlock(), countMatches()
this is still WIP and does not work yet
corrected logic error
checkstyle fixes and further refactoring
all TestVHDLCodeGenerator test cases refactored
Merge pull request #165 from mtrberzi/backend-tests

Backend tests: AND, OR, NOT
Merge pull request #166 from maxqchen/master

Refactored out const fields