CPU hotplug, debug: detect imbalance between get_online_cpus() and put_online_cpus()

The synchronization between CPU hotplug readers and writers is achieved
by means of refcounting, safeguarded by the cpu_hotplug.lock.

get_online_cpus() increments the refcount, whereas put_online_cpus()
decrements it.  If we ever hit an imbalance between the two, we end up
compromising the guarantees of the hotplug synchronization i.e, for
example, an extra call to put_online_cpus() can end up allowing a
hotplug reader to execute concurrently with a hotplug writer.

So, add a WARN_ON() in put_online_cpus() to detect such cases where the
refcount can go negative, and also attempt to fix it up, so that we can
continue to run.

Change-Id: I144efeaa5899a2e8a3cddd21f010679cbaaa2459
Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Reviewed-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Git-commit: 075663d19885eb3738fd2d7dbdb8947e12563b68
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
ARM: dts: msm: add perf-events support for msm8226

Add the device definitions for the Cortex-A7
PMU on msm8226.

Change-Id: I8752ec03ddc3d6d21bf1b996e81eaca7fb57d8b4
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Fix counts across power collapse

After entry and exit from power collapse, the perf pm_notifier was
calling perf_pmu_disable/enable functions from perf core. Perf core
maintains a counter that it uses to match disable and enable calls but
since pm_notifier is invoked asynchronously, the counter was getting a
non-zero value which prevented the pmu from being enabled. As a result of
this, we were seeing zero counts for some cores across power collapse.

Make the architecture specific calls directly from pm_notifier.

Change-Id: I744e190906a20e70e1e4798235215c385018b121
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
ARM: dts: msm: add perf-events support for msm8x10, msm8x12

Add the device definitions for the Cortex-A7
PMU on msm8x10.

Change-Id: I0e45c01cec2c92e437cc11cee88777bca271b839
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Make per-process counters configurable

Add feature to enable/disable per-process tracecounters at run-time.

Change-Id: Id6a4c7a0ecd1f5add85464c6ed260860e15c4e3b
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
msm: perf: Add L2 support for tracecounters

Add L2 counter output to the tracecounters implementation.
This enables collection of L2 PMU counter values upon context switch.
Set up filtering based on number of L2 counters and number of cores.
Read L2 counter values and display them along with L1 counter values.

Change-Id: I8bbbd251ee52c66505d22ccf037c601013a916f0
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
msm: perf: clean up duplicate constraint events

Events with a duplicate constraint are set to state=OFF when detected,
so that their duplicate counts are not read. However, they were not being
cleaned up because the core code only cleaned up ACTIVE events.
This resulted in counters not being freed and eventually running out
of resources.

Clean up the events with state==OFF that were marked that way because of
constraint duplication.
Ensure counts are not updated for OFF events.

Change-Id: If532801c79e6ad6809869eb0a3063774f00c92c3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Signed-off-by: revjunkie <gadgetjuan@gmail.com>