Changed delta-sigma component for more registers and improved performance
Altered strobegen and cic_decim to avoid unregistered lock for clock enables
Adjusted for minor bug during synthesis
First synthesis atempted
Fanout limit at ce_adc to improve setup time
Added register in front of RAM to infer registered RAM
Bug in monit calculation corrected
Several minor changes to improve timing and debug
New signal generator for silicon tests
Removed generated files from index