schematics: DIP28-SKIINNY in library.
schematics: W65C22 (VIA) & UM61256AK-12 (SRAM) parts in library.
schematics: use parts newly imported into library.
schematics: 28C64 in library.
schematics: use 28C64 newly added to library.
schematics: 2x10 pin header for VIA port A and B.
schematics: 2x20 header for address + data bus.

Ground connections match those on a parallel ATA cable.  Thus a
40-connector 80-conductor (UDMA) cable can be used to interleave ground
wires between signal wires.

ADDRESS[0..15] here maps directly to DATA[0..15] in PATA.
schematics: .gitignore separated from main .gitignore
schematics: README.md has Notes / TODO.
schematics: README.md updates
schematics: ROM WE tied HIGH (disabled).
schematics: RWB connected 6502, 6522, RAM. Split named net.
schematics: bus lines closer to pins.
schematics: schematic component spacing / orientation tweaked.
schematics: OE and CE tied together, for ROM and RAM.
schematics: decoupling caps for all ICs; 0.1uF 0805 SMD.
schematics: frame has CNAME, CREVISION, DESIGNER attributes.
schematics: DS1813 library added.

Source:
ftp://ftp.cadsoft.de/eagle/userfiles/libraries/ds1813_revised.lbr
schematics: reset circuit (DS1813); no button yet.
schematics: crystal oscillator; half can.