Updated tested behavior to more closely match Verilog timing.
Merge branch 'master' into new_new_tester
Updating internal tests to reflect new tester behavior.
Passes all internal tests.
add trace command to debug api
Vtests: fix the api handler, making it easy to see VPDs
Vtests: add Mem waveforms
Vtests: add propagate & tick apis
Added support for --emitTempNodes to Flo backend.
Merged in more recent changes to master.
Merge pull request #234 from ucb-bar/new_new_tester

New emulator API behavior
Merge branch 'master' into wirewidthtypearithnamedparams
Remove scalpels/sponges from the patient.

Remove commented-out and debug code. Simplify some expressions to
reduce differences with master branch.