Initial
Initial
Initial
Decoder output stored
Initial
Initial
Initial
D1 v1 4-bit multiplier with 8 clock cycles
D1 v2 4-bit multiplier with 4 clock cycles (merged add & shift)
D1 v3 var(8)-bit multiplier, MachXO bi-direction port
D1 Remove unused Creg
D1 Test branches
Lab note urls
M4 pin assignments
D2 Remove other group's generated verilog file