During the simulation these needed to be in entity section
Question remains what happens during the FPGA build
Can they be in architecture Behavioral of std_sig is before the begin
still need a comb to test if the FsmUpdate_p works
currently in the TBstd_sig this is being done
		updated_x <= '1';
		sigDelayed_x <= '1';
		sam_addr_x <= b"00000000000001";
		addrjpeg_x <= b"10000000000001";
		addr_x <= b"10000000000001";
These signals are not part of simulation
    dataToRam_r,
    dataToRam_x
--Signals constants needed by FsmUpdate_p---------------------------------------
--signal addr_x : unsigned(13 downto 0) := (others => '0');
--signal sam_addr_x : unsigned(13 downto 0) := (others => '0');
--signal updated_x : std_logic := '0';
--signal sigDelayed_x : std_logic := '0';
--signal addrjpeg_x : unsigned(13 downto 0) := (others => '0');
--signal dataToRam_x : unsigned(15 downto 0) := (others => '0');
--signal addr_r : unsigned(13 downto 0);
--signal sam_addr_r : unsigned(13 downto 0) := (others => '0');
--signal updated_r : std_logic := '0';
--signal sigDelayed_r : std_logic := '0';
--signal addrjpeg_r : unsigned(13 downto 0) := (others => '0');
--signal dataToRam_r : unsigned(15 downto 0) := (others => '0');
--Signals constants needed by FsmUpdate_p---------------------------------------