Remove BitwiseOrAnd synonyms Or & And from source
Output SSA IR from GeneratorM

Static single assignment form contains
- Variables only assigned once (new)
- Every variable is assigned before use
Merge pull request #4 from aleksanb/output-ssa-asembly

Output SSA IR from GeneratorM
Merge pull request #3 from aleksanb/remove-or-and

Remove BitwiseOrAnd synonyms Or & And from source
Add RegisterAllocation skeleton
Add Linear-time register allocation!