ARMv7 register cache optimizations.
Enable support for not loading a destination register on FPR cache.
Dump registers if they won't be used later in the block. Stolen from Fiora.
Adds MCR/MRC to the ARMv7 emitter.
Implements block time profiling on ARMv7.

This was interesting implementing.
Our generic QueryPerformanceCounter function on ARMv7 was so slow that profiling a block was impossible.
I waited about five minutes and I couldn't even get a single frame to output.
This instead uses ARMv7's PMU to get cycle counts, which are a relatively minor performance drop in my testing.
One disadvantage of this method is that the kernel can lock us out of using these co-processor registers, but it seems to work on my Jetson board.
Another disadvantage is that we aren't having block times in "real" time but cycles instead, not too big of a deal.

This also removes instruction run counts from profiling because that's just annoying and we don't expose an interface for even getting those results
from our UI.