Ignorance
Removing app_obj, sim_src/obj_dir, sim_src_orig/obj_dir
First commit. Changes to debug interface. Pipeline misses very first branch/jump/whatever.

Conflicts:
	VMIPS
	VMIPS_bkp
	app_obj/noio_1.txt
	app_obj/noio_10.txt
	app_obj/noio_11.txt
	app_obj/noio_12.txt
	app_obj/noio_13.txt
	app_obj/noio_14.txt
	app_obj/noio_19.txt
	app_obj/noio_2.txt
	app_obj/noio_20.txt
	app_obj/noio_21.txt
	app_obj/noio_22.txt
	app_obj/noio_23.txt
	app_obj/noio_24.txt
	app_obj/noio_26.txt
	app_obj/noio_27.txt
	app_obj/noio_28.txt
	app_obj/noio_3.txt
	app_obj/noio_4.txt
	app_obj/noio_5.txt
	app_obj/noio_6.txt
	app_obj/noio_7.txt
	app_obj/noio_8.txt
	app_obj/noio_9.txt
	memoryWrites.txt
	sim_src/COMMIT.v
	sim_src/ID.v
	sim_src/IF.v
	sim_src/MIPS.v
	sim_src/REN.v
	sim_src/RF.v
	sim_src/obj_dir/VMIPS
	sim_src/obj_dir/VMIPS.cpp
	sim_src/obj_dir/VMIPS.h
	sim_src/obj_dir/VMIPS_MIPS.cpp
	sim_src/obj_dir/VMIPS_MIPS.h
	sim_src/obj_dir/VMIPS__ALL.a
	sim_src/obj_dir/VMIPS__ALLcls.o
	sim_src/obj_dir/VMIPS__ALLsup.o
	sim_src/obj_dir/VMIPS__ver.d
	sim_src/obj_dir/VMIPS__verFiles.dat
	sim_src/obj_dir/sim_main.o
	sim_src/obj_dir/verilated.o
	sim_src/sim_main.cpp
	sim_src_orig/ID.v
	sim_src_orig/IF.v
	sim_src_orig/obj_dir/VMIPS
	sim_src_orig/obj_dir/VMIPS_MIPS.cpp
	sim_src_orig/obj_dir/VMIPS__ALL.a
	sim_src_orig/obj_dir/VMIPS__ALLcls.o
	sim_src_orig/obj_dir/VMIPS__verFiles.dat
	sim_src_orig/obj_dir/sim_main.o
	sim_src_orig/sim_main.cpp
First commit. Changes to debug interface. Pipeline misses very first branch/jump/whatever.

Conflicts:
	VMIPS_bkp
	app_obj/noio_1.txt
	app_obj/noio_10.txt
	app_obj/noio_11.txt
	app_obj/noio_12.txt
	app_obj/noio_13.txt
	app_obj/noio_14.txt
	app_obj/noio_19.txt
	app_obj/noio_2.txt
	app_obj/noio_20.txt
	app_obj/noio_21.txt
	app_obj/noio_22.txt
	app_obj/noio_23.txt
	app_obj/noio_24.txt
	app_obj/noio_26.txt
	app_obj/noio_27.txt
	app_obj/noio_28.txt
	app_obj/noio_3.txt
	app_obj/noio_4.txt
	app_obj/noio_5.txt
	app_obj/noio_6.txt
	app_obj/noio_7.txt
	app_obj/noio_8.txt
	app_obj/noio_9.txt
	sim_src_orig/ID.v
	sim_src_orig/obj_dir/VMIPS
	sim_src_orig/obj_dir/VMIPS.cpp
	sim_src_orig/obj_dir/VMIPS_MIPS.cpp
	sim_src_orig/obj_dir/VMIPS_MIPS.h
	sim_src_orig/obj_dir/VMIPS__ALL.a
	sim_src_orig/obj_dir/VMIPS__ALLcls.o
	sim_src_orig/obj_dir/VMIPS__verFiles.dat
	sim_src_orig/obj_dir/sim_main.o
Added testbench file

Conflicts:
	sim_src/queue.v~
Created plumbing for queue

Conflicts:
	sim_src/obj_dir/verilated.d
	sim_src/obj_dir/verilated.o
Both original and development compiling.

Conflicts:
	VMIPS
	VMIPS_bkp
	app_obj/noio_1.txt
	app_obj/noio_10.txt
	app_obj/noio_11.txt
	app_obj/noio_12.txt
	app_obj/noio_13.txt
	app_obj/noio_14.txt
	app_obj/noio_19.txt
	app_obj/noio_2.txt
	app_obj/noio_20.txt
	app_obj/noio_21.txt
	app_obj/noio_22.txt
	app_obj/noio_23.txt
	app_obj/noio_24.txt
	app_obj/noio_26.txt
	app_obj/noio_27.txt
	app_obj/noio_28.txt
	app_obj/noio_3.txt
	app_obj/noio_4.txt
	app_obj/noio_5.txt
	app_obj/noio_6.txt
	app_obj/noio_7.txt
	app_obj/noio_8.txt
	app_obj/noio_9.txt
	memoryWrites.txt
	sim_src/obj_dir/VMIPS
	sim_src/obj_dir/VMIPS.cpp
	sim_src/obj_dir/VMIPS.h
	sim_src/obj_dir/VMIPS_MIPS.cpp
	sim_src/obj_dir/VMIPS_MIPS.h
	sim_src/obj_dir/VMIPS__ALL.a
	sim_src/obj_dir/VMIPS__ALLcls.d
	sim_src/obj_dir/VMIPS__ALLcls.o
	sim_src/obj_dir/VMIPS__ALLsup.cpp
	sim_src/obj_dir/VMIPS__ALLsup.d
	sim_src/obj_dir/VMIPS__ALLsup.o
	sim_src/obj_dir/VMIPS__Syms.cpp
	sim_src/obj_dir/VMIPS__Syms.h
	sim_src/obj_dir/VMIPS__ver.d
	sim_src/obj_dir/VMIPS__verFiles.dat
	sim_src/obj_dir/VMIPS_classes.mk
	sim_src/obj_dir/sim_main.d
	sim_src/obj_dir/sim_main.o
	sim_src_orig/obj_dir/VMIPS
	sim_src_orig/obj_dir/VMIPS.cpp
	sim_src_orig/obj_dir/VMIPS.h
	sim_src_orig/obj_dir/VMIPS.mk
	sim_src_orig/obj_dir/VMIPS_MIPS.cpp
	sim_src_orig/obj_dir/VMIPS_MIPS.h
	sim_src_orig/obj_dir/VMIPS__ALL.a
	sim_src_orig/obj_dir/VMIPS__ALLcls.d
	sim_src_orig/obj_dir/VMIPS__ALLcls.o
	sim_src_orig/obj_dir/VMIPS__ALLsup.cpp
	sim_src_orig/obj_dir/VMIPS__ALLsup.d
	sim_src_orig/obj_dir/VMIPS__ALLsup.o
	sim_src_orig/obj_dir/VMIPS__Syms.cpp
	sim_src_orig/obj_dir/VMIPS__Syms.h
	sim_src_orig/obj_dir/VMIPS__ver.d
	sim_src_orig/obj_dir/VMIPS__verFiles.dat
	sim_src_orig/obj_dir/VMIPS_classes.mk
	sim_src_orig/obj_dir/sim_main.d
	sim_src_orig/obj_dir/sim_main.o
	sim_src_orig/obj_dir/verilated.d
	sim_src_orig/obj_dir/verilated.o
Configuring what files are tracked
Commit.v formatting changes

Conflicts:
	sim_src/COMMIT.v
	sim_src/obj_dir/VMIPS_MIPS.cpp
	sim_src/obj_dir/VMIPS__ALL.a
	sim_src/obj_dir/VMIPS__verFiles.dat
More files ignored. Next: add debug info to ROB queue: show finished bit, branch bit, etc.

Conflicts:
	VMIPS
	memoryWrites.txt
	sim_src/ID.v~
	sim_src/RF.v~
	sim_src/queue.v~
	sim_src/sim_main.cpp~