Abstract buses

Separate logic from hardware access for I2C, SPI, GPIO peripherals. Now, driver logic to control various devices on the HackRF is independent of the particular peripherals and GPIO pins used to interact with them. This facilitates easier (and potentially dynamic) adaptation of code to new hardware -- imagine a single firmware image that runs on Jawbreaker *and* HackRF One. It also facilitates insertion of an operating system layer below the drivers. This layering also permits arbitration of a shared bus (e.g. the SPI bus where the MAX2837 and MAX5864 are located) so that client code needn't concern itself with switching the bus between peripherals (a feature for a future commit).

Code is moderately well tested. RX and TX, sample rate changes, tuning, CPLD programming, LEDs are all demonstrated functioning on a HackRF One after this change.