VHDL code generation: nets, registers

First step towards #120.

I feel kind of iffy putting this forward right now, but I wanted to have something to show for myself with regards to this. I also do not want to let this class get too large before making a PR, so this is about as much code as I want to have reviewed right now.

I wish there were more test cases (I always want more test cases) so maybe I will work on that in a bit. Regardless, here is code generation for VHDL, dealing with input and output pins and registers. I have another private branch that defines an entry point to this (with options etc.) and it creates a fake schematic and invokes the generator and yeah. With these commits we are generating real, synthesizable VHDL (even if it is not very interesting VHDL).
OMG WOW