target-arm: Don't expose wildcard ID register definitions for ARMv8

In ARMv8 the 32 bit coprocessor ID register space is tidied up to
remove the wildcarded aliases of the MIDR and the RAZ behaviour
for the unassigned space where crm = 3..7. Make sure we don't
expose thes wildcards for v8 cores. This means we need to have
a specific implementation for REVIDR, an IMPDEF register which
may be the same as the MIDR (and which we always implement as such).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8

Many of the reginfo definitions in cp_reginfo[] use CP_ANY wildcards.
This is for a combination of reasons:
 * early ARM implementations really did underdecode
 * earlier versions of QEMU underdecoded and we can't tighten
   this up because we don't know if guests really require this or not
 * implementation convenience

For ARMv8 the architecture has tightened things up and system and
coprocessor registers are always specifically decoded. We take
advantage of this opportunity for a clean break by restricting
our CP_ANY wildcarded reginfo to pre-v8 CPUs, and providing
specifically decoded versions where necessary for v8 CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement auxiliary fault status registers

Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Load ELF images with the correct machine type for CPU

When trying to load an ELF file specified via -kernel, we need to
pass load_elf() the ELF machine type corresponding to the CPU we're
booting with, not the one corresponding to the softmmu binary
we happen to be running. (The two are different in the case of
loading a 32-bit ARM ELF file into a 32 bit CPU being emulated
by qemu-system aarch64.) This was causing us to incorrectly fail
to load ELF images in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
This isn't really a big deal since we can just say "use the
qemu-system-arm binary instead".

Incidentally I suspect hw/i386/multiboot.c has a similar
problem where it calls load_elf() passing ELF_MACHINE.
target-arm: Implement AArch64 address translation operations

Implement the AArch64 address translation operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement RVBAR register

Implement the AArch64 RVBAR register, which indicates the reset
address. Since the reset address is implementation defined and
usually configurable by setting config signalso in hardware, we
also provide a QOM property so it can be set at board level if
necessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement Cortex-A57 implementation-defined system registers

Implement a subset of the Cortex-A57's implementation defined system
registers. We provide RAZ/WI or reads-as-constant/writes-ignored
implementations of the various control and syndrome reigsters.
We do not implement registers which provide direct access to and
manipulation of the L1 cache, since QEMU doesn't implement caches.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement CBAR for Cortex-A57

The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view, necessitating a 64-bit QOM property. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
I assume I can't expand the existing uint32_t QOM property to
uint64_t. The 32<->64 mapping hardcoded here is strictly
speaking impdef behaviour so it's possible future cores might
do something different; the alternative to hardcoding this
(and possibly converting the CBAR regdefs into impdef regdefs
in cpu64.c later) would be to require boards to set both
reset-cbar and reset-cbar64 properties separately...
target-arm: Make Cortex-A15 CBAR read-only

The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
qemu-log: correct help text for -d cpu

This doesn't just dump CPU state on translation but on every block
entrance.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
qemu-log: support simple pid substitution in logfile

When debugging stuff that occurs over several forks it would be useful
not to keep overwriting the one logfile you've set-up. This allows a
simple %d to be included once in the logfile parameter which is
substituted with getpid().

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
qemu-log: new option -dfilter to limit output

When debugging big programs or system emulation sometimes you want both
the verbosity of cpu,exec et all but don't want to generate lots of logs
for unneeded stuff. This patch adds a new option -dfilter which allows
you to specify interesting address ranges in the form:

  -dfilter 0x8000-0x9000,0xffffffc000080000+0x200,...

Then logging code can use the new qemu_log_in_addr_range() function to
decide if it will output logging information for the given range.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
qemu-log: make in_asm, out_asm and op_opt understand dfilter

This ensures the code generation debug code will honour -dfilter if set.

----

v2 (wip)
   - checkpatch updates
trace: teach lttng backend to use format strings

This makes the UST backend pay attention to the format string arguments
that are defined when defining payload data. With this you can now
ensure integers are reported in hex mode if you want.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2
  - remove silly debug statements

v3 (wip)
  - fix spelling
trace: add translate-block tracing support
target-arm: dump the correct cpu state when in AArch32 mode

Signed-off-by: Rob Herring <rob.herring@linaro.org>
target-arm: make arm_dump_cpu_state consistent with aarch64

The aarch64 dumper helpfully dumped PC and SP so make ARM32 do the same.
Also prefix the line with A32/64 to make grepping through gigabytes of
logs easier.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
target-arm: make arm/aarch64_cpu_dump_state honour dfilter

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
target-arm: A64: add stub hypercall handler (hvc)

Mainly as an excuse to add tracing
target-arm: add mmu tracing