msm: clock: Use CLKFLAG_NO_RATE_CACHE in clk_set_parent

Some use cases involve the rate of a parent changing
from under a child. Therefore the set_parent op needs
a chance to update the rate field. Use the
CLKFLAG_NO_RATE_CACHE to allow the clk_set_parent to
go through to the set_parent op.

Change-Id: Icaf48915322539c84ef522621e35dafebe08b23b
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm-camera: enable csi-ahb-clk while accessing csi phy registers.

Turning on csi_ahb_clk while accessing csi phy registers at boot
time to avoid boot time crashes.

Change-Id: I88474a99141036e5d1adb541545e22bda78dc01c
Signed-off-by: Aditya Jonnalagadda <ajonnala@codeaurora.org>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: rpm-regulator-smd: correct use-after-free in rpm_vreg_device_remove

Modify the rpm_vreg_device_remove() function so that the reg
pointer is not dereferenced after being freed.

Change-Id: I0bc2c38a00c5d6b783f52c0ae0f1faa31d3a1e4d
CRs-Fixed: 564463
Signed-off-by: David Collins <collinsd@codeaurora.org>
msm: clock-krait: Fix register checking for div clock

Fix the wrong operand used to mask divider bits.

Change-Id: If2be61dece01b8171b31938b3d7c14fb497c0fd3
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock-krait-8974: Add support for 8974 Krait clocks

The clock-krait-8974 driver uses the clock-krait library and models the
krait clock tree in MSM8974. The following data are read from device tree
the keep the driver more reusable:
- PVS tables for the CPUs and the L2 voltage table
- AVS configuration table
- HFPLL and efuse register bases
- Regulators used by the krait subsystem

Change-Id: I7b145c7f2361d93adbfbc2896040a19bf3be31a2
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait-8974: Run force reinit sequence for all CPUs

The HFPLL and krait mux force reinit sequence needs to be run for all CPUs
irrespective of whether they are online or offline. This is necessary to
ensure that when offline CPUs are brought online later on, they are brought
up at a known frequency.

To be able to do the above, we also have to remove the prepare count check
in krait core clock set rate ops. It's safe to do so since that check
wasn't really providing any additional protection on top of the checks
already done in the cpufreq driver.

Change-Id: Ia73459ee03d339c948d7f2ea9516df1c0d9b8bd0
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Always configure low performance level krait clock tree

With newer HW versions, switching between BHS and LDO power supplies also
switches the CPU between the high performance clock tree output and low
performance clock tree output respectively.

Since the low performance clock tree is never configured (since it was
never used before), with newer HW versions running the CPU off the LDO
supply would also run the CPU at an unknown frequency that could be higher
that the max frequency for that specific voltage/current level.

Fix this by always configuring the high performance clock tree and the low
performance clock tree to the same frequency. This change is also
compatible with HW versions that don't have a low performance clock tree
since the register bits that correspond to the low performance clock tree
are marked as unused/reserved.

Change-Id: Ie82bf735220619be7ffd496cbd8b017c89904b41
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-krait: Read CONFIG_CTL value and the vco mask from DT

The config control register may have different reset
values on different MSMs. Also, not all HFPLLS may need
to switch between VCO modes. Read both the config control
register initialization value and the VCO user control
mask from device tree.

Change-Id: I832ee3acaa7f4b7b0637d0732ddf275d9475e8bc
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
clock-krait-8974: Increase PVS bin efuse field to a 4-bit field

This also needs changes to the redundant fuse data field to support making
corrections to a 4-bit field.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Change-Id: Ia15e5375537ff587a502fae975fdf854d08fa083
msm: clock-krait-8974: Fall back to safest PVS when table not found

If there is new hardware that uses unexpected PVS/Speed bin bits, we
should fall back to the safest PVS table instead of failing to probe.
Implement this fall back during clock-krait-8974 probe.

Change-Id: Ie2b06839cac7e5e63eb99df69f9a0aa20744c6c5
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: clock: Call regulator_enable/disable when updating vdd

When all clocks on a regulator are disabled, regulator_disable should
be called.  Likewise, when first clock is prepared, regulator_enable
should be called.

Add regulator_enable/disable function during voltage voting.

Conflicts:

        arch/arm/mach-msm/clock.c

Change-Id: Id036e95a4807574ae143a83cf0280fd61635257f
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock: Don't update clk->parent in clk_set_parent()

Any change to the parent field has to be done between __clk_pre_reparent()
and __clk_post_reparent() to avoid race conditions. So, stop setting the
parent field and leave it to the ops->set_parent() implementations to
update the parent field. All current implementations of ops->set_parent()
already do so.

Change-Id: Idc41bee306881a885335ecb322a21509231048cc
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock: Allow set_parent on clocks without the set_parent op

Some use cases require that set_parent succeed on a clock
that actually has just one parent. If a clock doesn't expose
a set_parent op, but the requested parent is the same as the
current parent, return success.

Change-Id: I0cf3f1e6e982de5cc86eb408ca71a62466710ef1
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock: Check that round_rate is less than fmax

HW has maximum frequency requirements. Ensure that the clock frequency
returned from clk_round_rate() is within these limits.

Change-Id: I0d4ed5851fc1f9f76c0ad0622cc6609e64e5311f
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: clock: Add is_better_rate() helper function

The is_better_rate() function is meant for use in clk_round_rate()
implementations to check if one of the new possible rates is better than
the current best match for the round rate request.

Change-Id: Ifca1840b15ec6faf6031af35ca9d219f6b32c3bb
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-generic: Add support for recursive set parent to mux_clk

When there are a bunch of nested muxes and a consumer calls
clk_set_parent() on the top level mux, it's possible that the consumer
doesn't care if the new parent is an immediate parent to the top level mux
and just wants the output from the new parent. So, recursively search for
the new parent (if recursive set parent is enabled for the mux) and get the
output of the new parent even if it has to go through multiple levels of
consecutive muxes.

Change-Id: Ibf76f11587e7c00fe1d34ce956e5a73c8db73e65
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-generic: Refactor round rate code

Use helper APIs to simplify div_clk and mux_clk round rate code.

Change-Id: I148e53819f8ec73271d127b92780c7ae231cb126
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-generic: Update the rate field on mux parent change.

Changing the parent of a mux changes its rate to the rate of the new
parent.  So, update the rate field of the clock when changing the parent of
the clock.

Change-Id: Ib219a5eb025c5bde922eed1864ce5296c7e84a8d
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm: clock-generic: Introduce an ext_clk clock type

Some clock controllers have input clock signals from
other clock controllers or hardware blocks. To model
these exterior signals, introduce an ext_clk type that
just passes requests to its parent clock. The clock
controller using the ext_clk type will have to do a
clk_get to get a handle to the external clock, and set
that as the parent on the ext_clk clock.

Change-Id: I762f7b4663d5a55d95e5d3b6808004b77b58e2da
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>