minor cleanup of cup alu comments/code
rename 'z' to 'zero' in alu.v to improve name
simplify *reggy* into single regr

Previously, there were several modules which provided register
functionality but they each varied in their options.  Some supported
stall, others supported zeroing, others supported both.  However
they were all very similar.

Simplify all the different register modules in to one module (regr)
which takes options clear/zero and hold/stall.
rename branch to branch_s2

Rename the branch signal to branch_s2 to make it clear what stage it is
coming from.
bring out alu zero signal for branch calculation

Previously, the zero signal was not brought out of the alu module.
Bring it out in stage 3 and register it to stage 4 as well.

The zero signal will be needed in stage 4 for branch calculations.
fix branch calculation, move to stage 4

Move branch calculation from stage 2, which incorrectly just compared
the register addresses, to stage 4 where it has access to the value of
the register.  Flush stage 3, in addition to 1 and 2, when a branch
occurs.
create .hex and don't delete

Previously the Makefile for verilog/test would create the .hex
files but then delete them since they were a secondary target.
Make them an explicit target so they are not deleted.
update test bench .check files