Staring the Moo'ification of VIC and using Roles to define chip features
adding the validate function and it is now much smaller
getting the digital_output function to work
implementing basic GPIO work. test 01 passes now
each operation is now split into a separate module to allow for breakup of
functionality without reducing complexity
Adding the delay() functions to the operations module
Will now divide the functions into separate files like the Roles allowing for
loading of only the required elements as needed. Also simplifies the codebase to
be in separate modules for ease of debugging and reference
test 03 is now complete. adding the ror/rol ops too
moving chip_config into the Chip functions as opposed to being a field
Updating GPSim code to also use the latest format of the code
Adding a separate module for all operators. delay has been moved to operations.
updating the GPIO implementation to allow for input-only and output-only port
selection explicitly. bi-directional ports are now explicit
Adding ADC support
ISR and Timer functionality is now complete for P16F690
fixing a missing check in write()
Adding the code for the handling of tables and pWM with some hacks