refine pNzc set access
Do full register loads instead of single-lane loads in DeblockLumaEq4H_neon

Instead of loading the registers one lane at a time, load full
registers and then transpose them.

This is faster, reducing the runtime for the function from about
506 cycles to 434 cycles (tested on a Cortex A8).

This also avoids an issue which seems like a cpu bug, present
on Sony Xperia T (cpu implementer 0x51 architecture 7 variant 0x1
part 0x04d). On such a device, it seemed like the "vswp q9, q10"
could start executing before the previous
vld4.u8 {d20[x],d21[x],d22[x],d23[x]}, [r3], r1
had finished and written back their result. Changing the
"vswp q9, q10" into "vswp q10, q9", or into separate
"vswp d18, d20; vswp d19, d21" (or the other way around) seemed to
avoid the issue. This happened occasionally (a couple times per
100000 invocations or so).
Merge pull request #755 from licaiguo/refine-pNzc

refine pNzc set access
Merge pull request #759 from mstorsjo/deblock-neon-transpose

Do full register loads instead of single-lane loads in DeblockLumaEq4H_neon