Implement PCMPxSTRx cases 0x0E, 0x34, 0x14, and reformat some of the
associated switch statements.  Fixes #326469, #327639, #328878
respectively.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2864 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips64: Support for Cavium MIPS Octeon Atomic and Count Instructions.

Implement Cavium MIPS specific instructions:
baddu, pop, dpop, saa, saad, laa, laad, lai, laid, lad, ladd, law, lawd,
las, lasd, lac, lacd

Fixes BZ #327223.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2865 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Support movi_{16b,8b}_#imm8.  Fixes #335262.  (dimitry@google.com)



git-svn-id: svn://svn.valgrind.org/vex/trunk@2866 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Support the "ishst" variant of "dmb".  Fixes #335263.  (dimitry@google.com)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2867 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Support ADC/ADCS/SBC/SBCS.  Fixes #335496.  (dimitry@google.com)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2868 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: Fix non mips compiler warning.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2870 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Reimplement the SIMD and FP instruction decoder, so as to avoid huge
amounts of duplicated decode, and to follow the documentation more
closely.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2871 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Move remaining implemented SIMD instructions into the new SIMD/FP
decoding framework.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2872 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove the old SIMD decoder entirely.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2873 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement FMUL 2d_2d_d[], 4s_4s_s[], 2s_2s_s[].


git-svn-id: svn://svn.valgrind.org/vex/trunk@2874 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement LD1R (single structure, replicate).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2875 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove temporary front end scaffolding for Cat{Even,Odd}Lanes
and Interleave{LO,HI} operations, and instead generate real
UZP1/UZP2/ZIP1/ZIP2 instructions in the back end. 



git-svn-id: svn://svn.valgrind.org/vex/trunk@2876 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement: abs d_d, neg d_d, abs std7_std7, addhn, subhn, raddhn, rsubhn


git-svn-id: svn://svn.valgrind.org/vex/trunk@2877 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: implement: addp std7_std7_std7, addv vector, addp d_2d


git-svn-id: svn://svn.valgrind.org/vex/trunk@2878 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement: orr_{8h,4h}_imm8_shifted, orr_{4s,2s}_imm8_shifted,
bic_{8h,4h}_imm8_shifted, bic_{4s,2s}_imm8_shifted, cls_std6_std6,
cm{eq,ge,gt,hi,hs,tst}_d_d_d, cm{ge,gt,le,lt}_d_d_zero,
cnt_{16,8}b_{16,8}b



git-svn-id: svn://svn.valgrind.org/vex/trunk@2879 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement: dup_{d_d[], s_s[], h_h[], b_b[]}, ext


git-svn-id: svn://svn.valgrind.org/vex/trunk@2880 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Increase the number of vector registers available for allocation from
3 to 5.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2881 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix an enum type confusion, PPCAvFpOp vs PPCAvOp, as excellently
detected by Clang.  Gcc, are you paying attention?


git-svn-id: svn://svn.valgrind.org/vex/trunk@2882 8f6e269a-dfd6-0310-a8e1-e2731360e62c
arm64: more SIMD instructions:
ins (vec[], vec[])
mla, mls, mul (vec, vec, vec[])
various more movi/mvni cases
not 16b/8b



git-svn-id: svn://svn.valgrind.org/vex/trunk@2883 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Implement LD1/ST1 {3 regs . 16b}, [ea]  (no offset)


git-svn-id: svn://svn.valgrind.org/vex/trunk@2884 8f6e269a-dfd6-0310-a8e1-e2731360e62c