AArch64/ARM64: support indexed loads/stores on vector types.

While post-indexed LD1/ST1 instructions do exist for vector loads,
this patch makes use of the more flexible addressing-modes in LDR/STR
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207838 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: refactor NEON post-indexed loads & stores (MC).

Previously, LLVM had no knowledge that these instructions actually
modified their address register: fine if they never end up in CodeGen,
but when I'd rather like to write some patterns for them it becomes a
disaster.

The change is mostly straightforward, I think the most significant
design decision was to *always* put the address write-back first. This
allows loads and stores to be accessed more uniformly, for example
permitting the continued sharing of the InstAlias definitions.

I also discovered that the custom Decode logic is no longer needed, so
I removed it.

No tests, because there should be no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207839 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64/ARM64: add patterns for post-indexed ST1 ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207840 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Only create one instruction when spilling/restoring register v3

The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.

v2:
  - Fix calculation of lane index
  - Extend VGPR liveness to end of program.

v3:
  - Use SIMM16 field of S_NOP to specify multiple NOPs.

https://bugs.freedesktop.org/show_bug.cgi?id=75005

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Expand TruncStore i64 -> {i16,i8}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207844 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Expand vector sin and cos.

v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Add processor type for Mullins.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207846 91177308-0d34-0410-b5e6-96231b3b80d8
Add a description for AMD's bdver4 (aka Excavator).

This is just bdver3 + AVX2 + BMI2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207847 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombine: prevent formation of illegal ConstantFP nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207850 91177308-0d34-0410-b5e6-96231b3b80d8
MC: place .file records into the correct section

.file records are supposed to have a section identifier of 65534
(IMAGE_SCN_DEBUG) rather than 0.  This is spelt out clearly within the PE/COFF
specification.  Fix this minor oversight with the implementation for support for
.file records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207851 91177308-0d34-0410-b5e6-96231b3b80d8
[GVN] Pass the phi-translated address of a load instead of the untranslated
address to AnalyzeLoadFromClobberingLoad. This fixes a bug in load-PRE where
PRE is applied to a load that is not partially redundant.

<rdar://problem/16638765>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207853 91177308-0d34-0410-b5e6-96231b3b80d8
Teach GlobalDCE how to remove empty global_ctor entries.

This moves most of GlobalOpt's constructor optimization
code out of GlobalOpt into Transforms/Utils/CDtorUtils.{h,cpp}. The
public interface is a single function OptimizeGlobalCtorsList() that
takes a predicate returning which constructors to remove.

GlobalOpt calls this with a function that statically evaluates all
constructors, just like it did before. This part of the change is
behavior-preserving.

Also add a call to this from GlobalDCE with a filter that removes global
constructors that contain a "ret" instruction and nothing else – this
fixes PR19590.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207856 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207857 91177308-0d34-0410-b5e6-96231b3b80d8
[tablegen] !strconcat accepts more than two arguments but this wasn't documented or tested.

Summary:
* Updated the documentation
* Added a test for >2 arguments
* Added a check for the lexical concatenation
* Made the existing test a bit stricter.

Reviewers: t.p.northover

Reviewed By: t.p.northover

Subscribers: t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D3485

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207865 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-cov: Fix handling of line zero appearing in a line table

Reading line tables in llvm-cov was pretty broken, but would happen to
work as long as no line in the table was 0. It's not clear to me
whether a line of zero *should* show up in these tables, but deciding
to read a string in the middle of the line table is certainly the
wrong thing to do if it does.

I've also added some comments, as trying to figure out what this block
of code was doing was fairly unpleasant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207866 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up constructor logic and member access for LoopVectorizeHints.

There are public functions that mutate various members as well as
another private member already, so make all the members private to
avoid the discontinuity and add accessors for the values. Should
be no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207868 91177308-0d34-0410-b5e6-96231b3b80d8
Aliases are always definitions. Delete dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207869 91177308-0d34-0410-b5e6-96231b3b80d8
Satisfy GCC's urgent need for parentheses around ‘&&’ within ‘||’.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207871 91177308-0d34-0410-b5e6-96231b3b80d8
[sanitizers] Propagate the sanitizer options through to the lit context.
This makes it *really* easy to debug leaks FYI:

ASAN_OPTIONS=detect_leaks=1 ./bin/llvm-lit -v <path to test>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207874 91177308-0d34-0410-b5e6-96231b3b80d8
Try simplifying LexicalScopes ownership again.

Committed initially in r207724-r207726 and reverted due to compiler-rt
crashes in r207732.

Instead, fix this harder with unordered_map and store the LexicalScopes
by value in the map. This did necessitate moving the definition of
LexicalScope above the definition of LexicalScopes.

Let's see how the buildbots/compilers tolerate unordered_map::emplace +
std::piecewise_construct + std::forward_as_tuple...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207876 91177308-0d34-0410-b5e6-96231b3b80d8