sim/ddr_model/*: change folder structure

The DDR simulation folder structure has been changed
to accommodate different DDR models and options
hdl/testbench/*/*_acq_core_test/*: move virtex6 sim to specific folder

This will allow adding more wb_acq_core simulations more easily
and for different FPGA families.
hdl/testbench/*/wb_acq_core_test/*: add Artix 7 FPGA simulation

The main difference from the Virtex 6 simulation is the DDR3
generated controller.
hdl/sim/ddr_model/artix7/*: disable DDR3 model debug messages