ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T

The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198914 91177308-0d34-0410-b5e6-96231b3b80d8
ARM IAS: support GNU extension for ldrd, strd

The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198915 91177308-0d34-0410-b5e6-96231b3b80d8
ARM IAS: support #:{lower,upper}16: for GNU compatibility

The GNU assembler supports prefixing the expression with a '#' to indiciate that
the value that is being moved is infact a constant.  This improves the
compatibility of the integrated assembler's parser for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198916 91177308-0d34-0410-b5e6-96231b3b80d8
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198922 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Fix not to use %t.cachedir/%p.

%p is like X:\foo\bar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198926 91177308-0d34-0410-b5e6-96231b3b80d8
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198927 91177308-0d34-0410-b5e6-96231b3b80d8
lli: LLIObjectCache: Use llvm::sys::path to get dirname.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198928 91177308-0d34-0410-b5e6-96231b3b80d8
lli: Tweak CacheName not to contain DOS driveletter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198929 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/ExecutionEngine/MCJIT/lit.local.cfg: Add "AMD64" in the host_arch list.

FIXME: We should not take CMake's ${CMAKE_SYSTEM_PROCESSOR}...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198930 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Remove "REQUIRES:shell". This doesn't depend on shell's behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198931 91177308-0d34-0410-b5e6-96231b3b80d8
Sink add_llvm_library(gtest_main) to UnitTestMain/CMakeLists.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198933 91177308-0d34-0410-b5e6-96231b3b80d8
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198934 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198937 91177308-0d34-0410-b5e6-96231b3b80d8
Use 'w' instead of 'c' to represent the win32 mangling.

This change was requested to avoid confusion if we ever support non windows coff
systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198938 91177308-0d34-0410-b5e6-96231b3b80d8
Silence unused variable warning for non-asserting builds that was introduced in r198937.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198941 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix regression caused by r198914

The disassembler would no longer be able to disambiguage between the two
variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt,
ldrbt, strbt mnemonics as both versions indicated the disassembler routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198944 91177308-0d34-0410-b5e6-96231b3b80d8
Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198945 91177308-0d34-0410-b5e6-96231b3b80d8
Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8
SCEVRewriter: Optionally interpret constants in value map as SCEVConstant

An upcoming loop vectorizer commit will want to replace a SCEVUnknown(Value*)
by a SCEVConstant. This commit modifies the SCEVParameterRewriter to support
this. The SCEVParameterRewriter constructor can optionally specify to follow
this behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198949 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorizer: Handle strided memory accesses by versioning

 for (i = 0; i < N; ++i)
   A[i * Stride1] += B[i * Stride2];

We take loops like this and check that the symbolic strides 'Strided1/2' are one
and drop to the scalar loop if they are not.

This is currently disabled by default and hidden behind the flag
'enable-mem-access-versioning'.

radar://13075509

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198950 91177308-0d34-0410-b5e6-96231b3b80d8