hdl/*/generated/virtex6/*: (1/5) some fixes and enhancements

This patch introduces the following changes
and enhancements:

* Add valid signal for qualifying position
  data at all rates

* Fix off-by one bug caused by the multiplexing module
  (TDM), due to a registering stage

* Improved amplitude of CIC blocks outputs. Now we use full
  precision and manually truncate and round to the target
  number of bits

* Enhanced Monitoring chain by removing unnecessary delays

* Change Delta-Sigma modules to use Radix2 divider algorithm
  instead of High-Radix. We got a roughly decrease of 99 (11 per
  divider) in DSP48 usage blocks


Former-commit-id: f809ea80e0712578ea7b24e451c945c77a02f343
hdl/*/position_calc/position_calc.vhd: (2/5) some fixes and enhancements

Change wrapper module to match new set of valid signals


Former-commit-id: 74378be41e50d2f2a1b50d6e309dcdebda725c1a
hdl/*/wb_position_calc/*: (3/5) some fixes and enhancements

Add new set of valid signals and implement set of FIFOs
to cross the fs_clk2x to fs_clk domain safely by using
async fifos.

Also, it is easier to use position data at any rate now by
simply checking the valid signal. Although the usage of the set of
Clock Enable (CE) signals would be beneficial from the timing
point of view, as multi-cycle constraints would apply.


Former-commit-id: fa724571c4cb2fb894eb1c3915c79cd54c02e3ec
hdl/modules/dsp_cores_pkg.vhd: (4/5) some fixes and enhancements

Add new interface of all modules to match the declaration


Former-commit-id: a189f93f279419ff292eb17d2ed977d4bc02f36a
models/*: (5/5) some fixes and enhancements

Add modified sysgen models with the fixes described in
an earlier commit


Former-commit-id: 843c8ceb4f92b57428ac6d62f8cc05e2a0d4c757
hdl/modules/wb_position_calc/*: removed .ucf file

This was causing error on designs that included dsp-cores,
but did not used the wb_position_calc module. Now the .ucf file
is kept here as a reference (as a .txt file), but it should be
coied to your top folder design and added as a .ucf file


Former-commit-id: acfc59d620619a0e6ce3b333236d44e4096dbb25
hdl/modules/wb_un_cross/*: fix bpm_swap reset interface

This signal was missing the last commits


Former-commit-id: fa0c8a9582106beab65b64d778f1a579e34f4492
hdl/modules/position_calc/*/virtex6: major bug fix

This patch fixes a major bug introduced in the last
big change (from commit 234fd2d503 [formerly f809ea80e0] to commit cfbdfdfa96 [formerly 843c8ceb4f]).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.


Former-commit-id: 929200ca2a2d157d47742d9bbe38b9025639694d
hdl/modules/position_calc/*/artix7: add artix7 files and major bug fix

This introduces the latest changes from commit
234fd2d503 [formerly f809ea80e0] to commit cfbdfdfa96 [formerly 843c8ceb4f] to artix7 FPGAs.

This patch also fixes a major bug introduced in the last
big change (234fd2d503 [formerly f809ea80e0] to commit cfbdfdfa96 [formerly 843c8ceb4f]).

* Change Delta-Sigma FIFO to Standard FIFO, instead
  of FWFT FIFO

* Only read from FIFO when not empty, as required by
  Sysgen. Otherwise, it gives an error.


Former-commit-id: f9d92c7364edfd31c58dfdbca8eb582630da5b16
models/*: new sysgen model to match latest fixes


Former-commit-id: 7f2aecd0e8d095b61cf921862eb28b264a6f795c
hdl/modules/position_calc/virtex6/*: fix sum output

The sum position data was wrongly truncated and its
value was wrong. A reiterpret block was added before
the cast block to correct this.


Former-commit-id: ba955ce3bb66502b75200f23827e866c3cd95b53
hdl/modules/position_calc/artix7/*: fix sum output

The sum position data was wrongly truncated and its
value was wrong. A reiterpret block was added before
the cast block to correct this.


Former-commit-id: 243f5b2df7caa8def4dd7d8c69328551b1702613
models/*: fix model to fix sum output at various rates


Former-commit-id: 94ab1b40589ec119755a17b392b75946bf97f5eb
hdl/*/position_calc/*/virtex6/*: fix monit 1 Hz output

This bug was due to the wrong reinterpret fixed point
in sysgen. The soulution was to reinterpret the intput
to the Decimation filter as FIX25_24.


Former-commit-id: 50f5bc7f24be7522838d86d11fe7a0f70db94611
hdl/*/position_calc/*/artix7/*: fix monit 1 Hz output

This bug was due to the wrong reinterpret fixed point
in sysgen. The soulution was to reinterpret the intput
on the Decimation filter as FIX25_24.


Former-commit-id: cd2802a6e555f4e0335cde60ebbb60a0a941d788
models/*: update sysgen model to match the last bugfix


Former-commit-id: 1d63321ae73e456937d5532680810b390e149e9f
hdl/modules/position_calc/*/virtex6/*: Fix Monit 1 Hz sum output


Former-commit-id: a190c09e4d67c8f5d4039b7dbdd49ee9c88c1896
hdl/modules/position_calc/*/artix7/*: fix Monit 1 Hz sum output


Former-commit-id: 37fd7f0425a8032929d4052d09896cb7e58844a1
models/ddc_bpm_476_066.mdl: fix Monit 1 Hz sum output


Former-commit-id: 9512548718ad4da296921f0c02339af8f79d5696
hdl/modules/position_calc/*/virtex6/*: fix mixed Monit 1 Hz outputs


Former-commit-id: 4ee9e8a57f59d0d7676a4ce5a77298d98f326e37