diff --git a/simics-workspace/modules/afdxES/packet-frame.dml b/simics-workspace/modules/afdxES/packet-frame.dml
index 57479cb..25c88ed 100644
--- a/simics-workspace/modules/afdxES/packet-frame.dml
+++ b/simics-workspace/modules/afdxES/packet-frame.dml
@@ -239,13 +239,20 @@ method send_frame_fragment(Afdx_Frame_Packet* afdx_frame_packet) {
 }

 method init_event() {
-	local uint8 k = 0;
-	for (; k < 128; ++k) {
+	local uint8 i = 0;
+    local double bag;
+
+	for (; i < $vl_enable_info.enable_num; ++i) {
 		local dbuffer_t *dbuf = new_dbuffer();
 		local uint8 *index = dbuffer_append(dbuf, sizeoftype(uint8));
-
-		*index = k;
-		inline $send_frame.post($scheduling_cfg_ram_array[k].BAG / 1000000, index);
+
+        if ($scheduling_cfg_ram_array[i].BAG == 0) {
+            bag = 0.005;
+        } else {
+            bag = $scheduling_cfg_ram_array[i].BAG / 1000000;
+        }
+
+		inline $send_frame.post(bag, &($vl_enable_info.vl[i]));
 	}
 }

diff --git a/simics-workspace/modules/afdxES/pci-register.dml b/simics-workspace/modules/afdxES/pci-register.dml
index adee6f9..16fbfed 100644
--- a/simics-workspace/modules/afdxES/pci-register.dml
+++ b/simics-workspace/modules/afdxES/pci-register.dml
@@ -522,7 +522,8 @@ bank pciport{
             switch ($middleware_mode) {
             case To429Middleware:
                 call $QuickSortAnalyseCamArray($analyse_cfg_cam_array);
-                call $QuickSortRMCamArray($rm_cfg_cam_array);
+                call $QuickSortRMCamArray($rm_cfg_cam_array);
+                call $InitVLEnableInfo();
                 break;
             case To664Middleware:
                 call $LoadCfgTo664Middleware();
diff --git a/simics-workspace/modules/afdxES/vl.dml b/simics-workspace/modules/afdxES/vl.dml
index 1b1659e..a85bd7c 100644
--- a/simics-workspace/modules/afdxES/vl.dml
+++ b/simics-workspace/modules/afdxES/vl.dml
@@ -2,6 +2,7 @@ dml 1.2;

 import "queue.dml";
 import "constant.dml";
+import "config-tables.dml";

 struct VL {
 	Queue sub_queue[4];
@@ -12,6 +13,13 @@ struct VL {

 data VL vl[128];

+struct VL_Enable_Info {
+    uint8 enable_num;
+    uint8 vl[128];
+}
+
+data VL_Enable_Info vl_enable_info;
+
 struct PHY_FIFO {
     Queue queue;
 }
@@ -33,3 +41,20 @@ method init_vl_cfg() {
         $recv_vl[i].expect_sn = 0;
     }
 }
+
+method InitVLEnableInfo() {
+    local uint32 i;
+    local uint32 j;
+
+    for (i = 0; i < $transmit_cfg_ram_index; ++i) {
+        for (j = 0; j < $vl_enable_info.enable_num; ++j) {
+            if ($transmit_cfg_ram_array[i].ram_data_part1.VL_INDEX == $vl_enable_info.vl[j]) {
+                break;
+            }
+        }
+        if (j == $vl_enable_info.enable_num) {
+            $vl_enable_info.vl[j] = $transmit_cfg_ram_array[i].ram_data_part1.VL_INDEX;
+            $vl_enable_info.enable_num++;
+        }
+    }
+}
diff --git a/simics-workspace/modules/afdxES2/afdxES2.dml b/simics-workspace/modules/afdxES2/afdxES2.dml
index b4b931b..0039425 100644
--- a/simics-workspace/modules/afdxES2/afdxES2.dml
+++ b/simics-workspace/modules/afdxES2/afdxES2.dml
@@ -184,6 +184,7 @@ implement load_cfg_table {
     method load_cfg_done() {
         call $QuickSortAnalyseCamArray($analyse_cfg_cam_array);
         call $QuickSortRMCamArray($rm_cfg_cam_array);
+        call $InitVLEnableInfo();
     }
 }

diff --git a/simics-workspace/modules/afdxES2/packet-frame.dml b/simics-workspace/modules/afdxES2/packet-frame.dml
index eb65f60..31ccd5b 100644
--- a/simics-workspace/modules/afdxES2/packet-frame.dml
+++ b/simics-workspace/modules/afdxES2/packet-frame.dml
@@ -213,16 +213,21 @@ method send_frame_fragment(Afdx_Frame_Packet* afdx_frame_packet) {
 }

 method init_event() {
-	local uint8 k = 0;
-	for (; k < 128; ++k) {
-        log "info" : "event";
+	local uint8 i = 0;
+    local double bag;
+
+	for (; i < $vl_enable_info.enable_num; ++i) {
 		local dbuffer_t *dbuf = new_dbuffer();
 		local uint8 *index = dbuffer_append(dbuf, sizeoftype(uint8));
-
-		*index = k;
-        inline $send_frame.post(0.01, index);
-		//inline $send_frame.post($scheduling_cfg_ram_array[k].BAG / 1000000, index);
-	}
+
+        if ($scheduling_cfg_ram_array[i].BAG == 0) {
+            bag = 0.005;
+        } else {
+            bag = $scheduling_cfg_ram_array[i].BAG / 1000000;
+        }
+
+		inline $send_frame.post(bag, &($vl_enable_info.vl[i]));
+	}
 }

 method init_phy() {
@@ -314,11 +319,6 @@ event send_phy {
                 }
                 break;
             case 3:
-                // for test begin
-                //og "info" : "interface_id = %d", interface_id;
-                //log "info" : "The phy_max_bandwidth = %d", $phy_max_bandwidth;
-                //while(1);
-                // for test end
                 if ((item_size + $phyA_already_send_byte <= $phy_max_bandwidth) &&
                     (item_size + $phyB_already_send_byte <= $phy_max_bandwidth)) {
                     call $DeQueue(&$phy_queue.queue, &item);
diff --git a/simics-workspace/modules/afdxES2/vl.dml b/simics-workspace/modules/afdxES2/vl.dml
index 708ffee..5e49caf 100644
--- a/simics-workspace/modules/afdxES2/vl.dml
+++ b/simics-workspace/modules/afdxES2/vl.dml
@@ -11,6 +11,13 @@ struct VL {

 data VL vl[SEND_VL_NUM];

+struct VL_Enable_Info {
+    uint8 enable_num;
+    uint8 vl[128];
+}
+
+data VL_Enable_Info vl_enable_info;
+
 struct PHY_FIFO {
     Queue queue;
 }
@@ -32,3 +39,20 @@ method init_vl_cfg() {
         $recv_vl[i].expect_sn = 0;
     }
 }
+
+method InitVLEnableInfo() {
+    local uint32 i;
+    local uint32 j;
+
+    for (i = 0; i < $transmit_cfg_ram_index; ++i) {
+        for (j = 0; j < $vl_enable_info.enable_num; ++j) {
+            if ($transmit_cfg_ram_array[i].ram_data_part1.VL_INDEX == $vl_enable_info.vl[j]) {
+                break;
+            }
+        }
+        if (j == $vl_enable_info.enable_num) {
+            $vl_enable_info.vl[j] = $transmit_cfg_ram_array[i].ram_data_part1.VL_INDEX;
+            $vl_enable_info.enable_num++;
+        }
+    }
+}