current setting the signals
even_odd_s & fwd_inv_s to true.
 even_odd_s <= '1';
 fwd_inv_s <= '1';

  112   429    56 1 1  -130  -130
results are the same between the local and FPGA
   79   350   395 1 1  -293  -293
goal is set these with the signals
  alias even_odd_tmp_s is  tojpeg_s(51);
  alias fwd_ins_tmp_s is tojpeg_s(52);
  even_odd_s <= even_odd_tmp_s(0);
  fwd_inv_s <= fwd_inv_tmp_s(0);