added input/output bus widths
finished first draft scalar reg file
removed random test wire
started VADD module
rewrote scalar reg file and continued with ALU
finished step 1 and 2 from http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/BinMath/addFloat.html for VADD
first pass VADD complete
Merge branch 'Max'