Changed up the SPI SRAM driver so that it automatically handles changing over to different chips, allowing the cache module to not have to worry about it AT ALL; it just uses raw address aligned to 0 and has no concept of chips. Started work on getting SPI flash to the same point, but not done yet. This is still all untested. Also changed the cache module to take in the external SPI SRAM address as a pointer parameter, allowing it to use address 0x00000000.