Rework atse_rx_cycles handling: count packets instead of fills, and use the
limit only when polling, not when in interrupt mode.  Otherwise, we may
stop reading the FIFO midpacket and clear the event mask even though the
FIFO still has data to read, which could stall receive when a large packet
arrives.  Add a comment about races in the Altera FIFO interface: we may
need to do a little more work to handle races than we are.

With this change, interrupt-driven use of the Alter triple-speed MAC now
appears to work reliably in casual testing; not yet enabled by default.
However, I am now experiencing a possible pipeline wedge in the 20140701
bitfile that needs diagnosing.