pipeline initial commit
Merge branch 'singlecycle' into pipeline
added altera debug ports to mapped
no longer need to load memory synthesize can do it
fixed instantiation of rf if as i removed clk and reset from the interface
added program instantiation and removed initialization from nRST
added tb module ports to make using a program in tb easier
fixed system_fpga labels for hex displays
cleaned up cc if and updated system tb period
Changed ram and system.sv files to CPUCLK/RAMCLK
fixed address range issue with ram, now have full range 0 - 0xFFFF
changed system name from CPU to SYS
updated ram file
Mergesort.asm added
Merge branch 'singlecycle' of /home/ecegrid/a/ece437l/git/studentlabs into riley
Merge branch 'pipeline' of /home/ecegrid/a/ece437l/git/studentlabs into riley

Conflicts:
	source/system.sv
	testbench/register_file_tb.sv
Made this shit compile.