ASoC: msm: qdsp6v2: Release IPA mapping

When DSP has a SMMU associated with it, audio driver will allocate
(KVA)kernel virtual address and (IPA)intermediate physical
address.When freeing memory audio driver should release IPA and KVA
mappings. Change fixes the issue where IPA mapping was not released

Change-Id: Id81ef9f2af29f2b6793853d8d0a1ef960c5d6310
CRs-fixed: 600938
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
power: qpnp-charger: wake up upon fast charge after resuming

When state of charge based charge resume happens there is
a delay between enabling charging again in hardware and
the fast charge state being reached. During this time
the system may have gone to suspend and the necessary
information is not conveyed to userspace.

Fix this by enabling the fast charge interrupt as a
wakeup interrupt when the SOC based resume event occurs.
Disable it when within the fast charge interrupt handler.

Change-Id: I286b1c12dbf057de974afb4084d92c157f08eee4
CRs-Fixed: 606012
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
hwmon: qpnp-adc-current: Add temperature compensation

Add temperature compensation parameters for PM8026 2.1.
Compensate the vbatt voltage for temperature variance above
25degC. Add similar compensation for current compensation.

Also update using the revid api's to check for PMIC revision
instead of using peripheral revision registers. Using
revid PMIC api's makes it easy to follow on what PMIC versions
are the temperature compensation being applied to. Depending
on VADC/IADC revision registers alone may not suffice since
there is no correlation between the individual peripheral
revision and the PMIC number. You could have the same
VADC revision on different PMIC's and to avoid such a scenario
use the PMIC revid.

Change-Id: I90adb1130b2e2461f762df774ddcd018e806cf78
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
ARM: dts: msm: Add phandle to read PMIC rev-id

The VADC/IADC peripheral need to read the PMIC type
and revision to apply the corresponding coefficients
for temperature compensation to vbatt and current.
The property is optional since there are few PMIC
VADC/IADC peripherals that don't have temperature
compensation coefficients added and during such
conditions the temprerature compensation is not
applied for those channels.

Change-Id: I5229934bec71b86f923042af943a3e080ceb009b
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
qpnp-pmic: revid: Add PMIC revision ID support

Add Revision ID support for PM8226 v2.2

Change-Id: Iadb13841bcfbbaa19642d541e5fb3f2a3f5a7544
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
hwmon: qpnp-adc: add PM8110 2.0 temperature compensation info

Add in support for PM8110 2.0 temperature compensation. Also, fix a few
bugs in the ADC compensation algorithm where 25C was treated as 2.5C.

Change-Id: Iafa3ceca2b5938432116ecc905dd54b2da7c4b0b
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
hwmon: qpnp-adc-current: fix current compensation direction

Currently the current compensation in the IADC driver is using the wrong
polarity. The compensation function is treating the current with the
battery being the source (i.e. discharging is positive and charging is
negative), but the IADC's IBAT readings treat the battery as a sink
(i.e. charging is positive and discharging is negative).

Fix this by reversing the sign of the iadc current readings before doing
compensation.

Change-Id: I1413ce491b1f430b6a78bfc480174321c512e289
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
hwmon: qpnp-adc-current: log the compensation coefficients

The compensation coefficients are used to execute performance tests.
Provide this information in the debug logs of the IADC driver.

Change-Id: I59df9501d8edf652c6cf0999a17cc820115b07cc
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
hwmon: qpnp-adc-current: Add temperature compensation

Add temperature compensation for IADC PM8026v2.2.
It shares the same temperature compensation parameters
as PM8026v2.1. The temperature compensation is required
on top of gain/offset calibration to compensate for
variations due to chip revision, manufacturer and
temperature.

Change-Id: Ic39ba249d8d28c36bf59d650dcc2c2a3889ee55b
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
hwmon: qpnp-adc-voltage: Add temperature compensation

Add VBAT and OCV temperature compensation for PM8026v2.2.
The temperature compensation is required on top of
gain/offset calibration to compensate for variations
due to chip revision, manufacturer and temperature.

Change-Id: I7c62340a74a118d6f80e4e6bba51c2d07c4a57c6
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
hwmon: qpnp-adc-voltage: Modify temperature compensation

Apply temperature compensation to minimum(die_temp, 60degC)
for vbatt compensation. For OCV temperature compensation
apply the compensation based on the die_temp for the
corresponding PMIC. The temperature compensation is
required on top of gain/offset calibration to compensate
for variations due to chip revision, manufacturer and
temperature.

Change-Id: I0826993ddebe7dae2f033d995fa1266f9509002c
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
hwmon: qpnp-adc-current: Fix offset channel selection

On PM8941 depending on the status of the BATFET
the reads on channel 0 for Internal RSENSE go to
channel 5 therefore the offset is performed on that
channel. This is applicable to only to PM8941 and
not on PM8026 and PM8110. Therefore apply the check
for offset channel selection based on the BATFET
status on PM8941 only.

Change-Id: I146b244c2b562664b85e804694f8d4b2aac3fa86
CRs-Fixed: 629758
Signed-off-by: Dipen Parmar <dipenp@codeaurora.org>
hwmon: qpnp-adc-current: Fix specifying batfet status

For the condition when PM8941 is true use the BATFET status
that is passed to the calibration api. Ignore the BATFET
status for all other PMIC versions.

For PM8941 when BATFET is open, the reads on channel 0 for
Internal RSENSE are redirected in HW to channel 0x5:
 EXTRSNS_OFFSET. Recalibrate based on this channel.

Change-Id: Ib0d477c5fb4537379b31faf1676d5956317b06a7
CRs-Fixed: 629758
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
ASoC: wcd9xxx: Set HPH PA register to volatile

Set HPH PA register to volatile to make sure the register will be
updated with proper bits during bringup

CRs-Fixed: 625324
Change-Id: I5a0caec730a902d6f8f251d5d87f407f9c1777ac
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
arm: arch_timer: set memory mapped timer interrupt as IRQF_TIMER

The memory mapped timer is used as a broadcast timer to wake the core for
timer interrupts when the arch timer might not be functional. When interrupt
is not marked as IRQF_NO_SUSPEND, the interrupt gets disabled during the
suspend_device_irqs() callback in the suspend path. If a core were to enter a
idle low power mode which relies on broadcast timer to process the interrupt,
the core is never woken up for timer interrupts.

Mark the interrupt with IRQF_TIMER which marks this interrupt as a timer
interrupt and also marks it as IRQF_NO_SUSPEND

CRs-fixed: 636712
Change-Id: I0484e92a9d05f66a0c5b3c00c584a3dd3fe6ae85
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
power: qpnp-bms: clamp for SOC <= 0

In some scenarios a negative soc may be calculated even
though VBAT is above the cutoff voltage.

The clamping function does not take negative SOC values
into account and fails to clamp the SOC. Fix this
by checking for SOC values <= 0.

CRs-Fixed: 623091
Change-Id: I8d64b3c8717e8088be71d84d66225512b85e87e3
Signed-off-by: David Keitel <dkeitel@codeaurora.org>
power: qpnp-bms: do not clamp SOC based on voltage when charging

The BMS driver currently reports SOC to be at least 1% whenever the
battery voltage is above cutoff voltage. However, this can cause an
issue when charging, where the IR drop across the battery causes the
battery terminal voltages to be higher than the cutoff even when the
battery is effectively dead. This makes the BMS driver always report 1%
when charging, even when it should be reporting 0%.

Fix this by not clamping the SOC when the battery is charging.

CRs-Fixed: 634856
Change-Id: I3d85b5b35973123471dc21eb9651c958219795f9
Signed-off-by: Xiaozhe Shi <xiaozhes@codeaurora.org>
ARM: dts: Modify BKE limiting for Krait master

Modify the BKE limiting properties for Krait master by setting up 2
levels of threshold checks and limiting bandwidth values to be applied.
These levels of throttling are needed in certain concurrency usecases to
protect real time masters from surges in bus usage from some APSS masters.

Change-Id: I04d086e10df27d0f7cc1a234fe9eb36a9ea73e65
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: msm_bus: Introduce multi level BKE limiting.

Introduce multi level BKE throttling for BIMC masters. By specifying an
array of thresholds and limiting bandwidth values, multiple levels of
master throttling can be achieved.

Change-Id: Ic3b483d3e987266e8f37e66dff8bedd49ddd1d4d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
iommu: msm: Add base physical address to drvdata structure

Add the physical address value to the iommu drvdata structure. This
address is needed for debugging purposes when we get iommu page
faults and during iommu halt and tlb sync issues.

Change-Id: I2d4f36cdfe8a3da772839cb07cd186820f2e1f52
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>