update to docs for dsp bootcamp
Some fixes and comments in getting started
Merge pull request #132 from schoeberl/master

Some fixes and comments in getting started
Fix Verilog backend regression introduced in f6bee8a4d930b613262addac8af91ed57ab1c329
check for assigning to non port inputs and make sure all module io are ports

Conflicts:

	src/main/scala/Bits.scala
	src/test/scala/DataTest.scala
merge
Fix assign-to-own-inputs test
check for assigning to non self or non parent outputs

Conflicts:

	src/main/scala/Bits.scala
flag illegal cross module references during trace

Conflicts:

	src/test/scala/ConnectTest.scala
Avoid Module.current popping an empty stack
Purposefully break ArbiterTest to force jrb to fix fire() XMRE bug
fix bug 100 -- make sure that io names are never overridden by wire names and that are only created from their io names
Merge branch 'master' of github.com:ucb-bar/chisel into dse