[FIX] Fix plkload to correctly handle multiple threads/irqs

For some drivers multiple IRQs and IRQ threads could exist. plkload
is fixed to work correctly even if there are several threads and
interrupts.

Change-Id: I0df74842bc14ea4d725dd59453c721aa97c7dfdf
[FIX]  Reimplement handling of PRes in transition DLL_CT4

Reimplement handling of PRes in transition DLL_CT4 in state
DLL_CS_WAIT_SOC as specified in EPSG 301. This covers the following
situations on CN implementations:
1. Just one SoC from MN is lost, because of EMI for example. So the
   next cycle starts with a PRes instead of SoC.
2. Multiple SoCs and the frames in between were lost, because of short
   cable disconnect for example (but frame timeout didn't occur yet).
   So the next cycle which is received by MN starts with a PRes.
3. A late PRes from another CN is received (PRes between SoA and SoC).
   On this CN this is handled as a loss of SoC, but the next SoC isn't
   actually lost. There is just a wrong PRes on the network.

The latter situation might be the reason why the PRes case has been
commented since the early versions of this stack. Why should one CN
care about mistakes of another CN? The answer is that the POWERLINK
network shall provide a deterministic real-time communication and
errors must not remain undetected.

Futhermore, with this fix we indirectly catch the case that an
openPOWERLINK MN (without further hardware support like frame
timestamps) cannot detect late PRes after the SoA. Now another CN
would increment its Loss-of-SoC error counter and force it to go back
to PreOp1 when the threshold is exceeded. For the user the root cause
of this error is a little bit hard to detect, but the error is unveiled
(if there are at least too CNs in the network).

Based on change for V1.8.4 by
Daniel Krueger <daniel.krueger@systec-electronic.com>

Change-Id: Ib5f41389bf4d43fd116e17a1256da43ceb92f14e
[FIX] Resolve Xilinx cmake filename case issue

This issue occures only on Linux where the case
of files is observed.

Change-Id: I2792b96af57c5c0eba729e11ab6a763bdd134065
[FIX] Add missing openMAC waveforms to documentation

Change-Id: If09aba765f4dac6e0dcc985235a827751db6e20f
[FIX] Fix MN issuing StatusRequest after NMTEnableReadyToOperate

If the MN issues an NMTCommand NMTEnableReadyToOperate the initial and
destination NMT state of the node must be NMT_CS_PRE_OPERATIONAL_2.
Therefore, it is not necessary to issue a StatusRequest frame after
C_NMT_STATE_TOLERANCE cycles monitoring the state change.
This change skips setting up the state change monitoring if the
initial and destination state is NMT_CS_PRE_OPERATIONAL_2.

Resolves: #838

Change-Id: I09bb1bfe7998b323f36a47835926a2a2bcae4c94
[FIX] Add missing interrupt dummy parameters for PCP

Define dummy values for HOSTIF_IRQ_IC_ID and HOSTIF_IRQ to avoid
compilation error in hostiflibint_microblaze.c.

Change-Id: I7b2610cd164e29b9917465e760ab3d6476943fe9
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Remove unwanted header inclusions that leads to compile error

Change-Id: Ibdb054dd631605d25ec74c0336f011ea7f9a5473
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Rework hardware cmake integration for dual processor systems

Rework hardware cmake work flow enabling dual processor designs.
- Introduce settings for PCP and HOST processor instance
- Adapt drivers and embedded CN demo
- Revise Xilinx eclipse project files

Change-Id: I3a449a1d9cbf1ae984eaaf7548c5d4730473f92b
[TASK] Add support in stack for Microblaze designs

Update Microblaze architecture sources for possible dual processor
designs.

Change-Id: I478af47bb9f7635e3160ece4c4e568ff50c8fe5a
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix Microblaze cn-gpio demo compilation error

- Add preprocessor definition for PCP designs to cn-gpio stack project
- Update processor instance check condition for Microblaze timer module

Change-Id: I430ce2117ba863cdd73db62205cc6b4d9c69d048
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix clock crossing ipcore

This commit solves clock transfer issues with commands in tight
sequences. The fast and slow clock domain instances are redesigned using
a state machine. The fast clock domain instance uses a dedicated signal
for synchronizing the slow clock domain state machine.

Change-Id: Id86edcd897c8dccd64957aaaa6ebe1658cc88373
[FIX] Fix Microblaze cn-gpio demo compilation error

- Update processor instance check condition for target-microblaze.c
- Update License information for stack liboplkcn CMakeLists.txt

Change-Id: I2fa23e0f657006607ebd02510e82062b7e062da5
Signed-off-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FEATURE] Add cross toolchain file for Xilinx ARM

Signed-off-by: Josef Baumgartner <josef.baumgartner@br-automation.com>
Change-Id: I582111ef3ce6f4618d1579d3d5c093a2cd7107f1
[FEATURE] Add Edrv module for Xilinx Zynq Gigabit Ethernet controller

Add edrv module for Xilinx Zynq Gigabit Ethernet controller (GEM).

Signed-off-by: Josef Baumgartner <josef.baumgartner@br-automation.com>
Change-Id: I3d7b7cbff735e4de033e73b2cd4db6c291255ec2
[FEATURE] Add high resolution timer module for Xilinx Zynq

Add high resolution timer module for Triple Timer Counter(TTC1) on
Xilinx Zynq SoC. The implementation is used for the Linux kernel
implementation of the stack.

Signed-off-by: Josef Baumgartner <josef.baumgartner@br-automation.com>
Change-Id: Id703d7066fb5f8a17bfba61288c08d85f20124af
[FEATURE] Add Xilinx Zynq support in Linux edrv module

Signed-off-by: Josef Baumgartner <josef.baumgartner@br-automation.com>
Change-Id: I2b8052d6bfadf90441bc8fdc853405dd7d9362b4
[FEATURE] Add documentation for Linux on Zynq ARM platform

Change-Id: Ied0aababf4309ac6b68463bc534b4dafeb5a4481
[TASK] Clean up oplk_sendAsndFrame()

Signed-off-by: Josef Baumgartner <josef.baumgartner@br-automation.com>

Change-Id: I1f074b8dd7d1cce4ee2edcb5dd5d9f3d5a3bc10e
[FIX] Add missing include in host interface driver

Change-Id: If8bafa6af2f409a2f501fcf91de7aaedf835f280
[TASK] Modify oplk_sendAsndFrame() to check async MTU

oplk_sendAsndFrame() checks if the size of the data to be sent
exceeds the maximum asynchronous frame size.

Change-Id: I42734e54d8f961325d280f489b608da4d85a7228