de1: Small cleanup
de1: Make simulations work again
de0_nano: Fix comments in wb_intercon.conf

Inline comments are broken when running current version of FuseSoC
under python3. Move them to separate lines for now
de0_nano: Restruture and regenerate wisbone interconnect

This patch removes the wb_data_resize blocks from orpsoc_top since
they are now generated in wb_intercon. It also puts the arbiter
between or1k data bus and the debug bus in a separate arbiter to
save some logic
de0_nano: Replace hardcoded rom with wb_ram component

wb_ram makes it easier to select a bootloader by just replacing the
memfile to load
de0_nano: Fix simulator support
de0_nano: Use hex instead of dec in intercon files
de0_nano: Drop aw param for wb_ram
de0_nano: Add missing connections in orpsoc_top.v
Revert "atlys: add timing constraints for dvi_gen CDC"

This reverts commit 081bf6253c8a9fcf6e906fd42bcbb691aa0e79ba.

On some versions of ISE, the build would fail with these
constraints present.
atlys: re-add pclk constraint

Contrary to what 7b02a538765b0ddbcbbd759b33312f786b491f39 said,
it seems like the build fails when either both the clk50mbufg
*and* the plk constraint is present or both are removed.

re-adding the pclk constraint makes the build succeed with
ISE 14.7 at least...
cores/mor1kx: remove mor1kx_rf_ram.v
Atlys: Add or1200 core.

fusesoc won't compie atlys system built with or1200 core instead of
mor1kx. This patch adds or1200 to be fetched if defined and place
or1200_defines.v locally as for othter board ports.
vlog_tb_utils: Added progress_bar function