Clean up Extract implementation
Support updating individual bits within Reg(UInt())

For example,

val foo = Reg(UInt(width = 10))
when (bar) { foo(baz) := quux }
big change for wrappers
Previous ROM switch to 'initial' was unsynthesizable - instead, we put the lookup code at each ROMRead instead of at ROMData, which now emits nothing.
Merge branch 'master' of https://github.com/ucb-bar/chisel
Use case statement for ROMs in Verilog

initial isn't supported by DC; always @(*) doesn't work in VCS because the
sensitivity list is never triggered.  Also, DC only appears to exploit
don't-cares (for non-power-of-2-depth ROMs) when case stataments are used.
kindly supports things bigger than 32bits
merge master