Add fix for data corruption issue

I found a bug that turned up when using the core in conjunction with the
Xilinx System Cache IP, in which memory data could be corrupted if the
master were to initiate a read and a write operation during exactly the
same clock cycle.  It was possible for the read address to be used for
the write operation, rather than keeping them properly isolated from
each other. This version now passes the memory tests properly when using
the System Cache IP.