devfreq: Add MSM CPUfreq governor

The MSM CPUfreq devfreq governor determines the CPU to DDR bandwidth vote
based on the current CPU frequency of all the active CPUs.

This functionality used to be a part of the MSM CPUfreq driver that
directly voted for the CPU to DDR bandwidth using MSM bus scaling APIs.
This refactor decouples CPU to DDR BW scaling from CPU frequency and allows
switch between various CPU BW governors.

The bandwidth values in the msm-cpufreq table have to be updated since the
new CPU BW driver does the MBps to Bps conversion correctly. The MSM
CPUfreq driver used to do * 1000 * 1000 to convert from MBps to Bps instead
of doing * 1024 * 1024.

Change-Id: I184f09d628a1b27d52506d2f760d65831f1a1110
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 4bbc993b178bca1969f2e4b122a32e0e589ee839)
devfreq: Add CPUBW HW monitor governor

The CPUBW HW monitor devfreq governor uses the Krait L2 PM counters to
determine the bandwidth needed by the Krait CPU subsystem. This governor
can be used in conjunction with the CPUBW devfreq device to dynamically
scale the DDR frequency based on the demand/actual usage from the Krait CPU
subsystem. Since this governor uses the Krait L2 PM counters it can
conflict with certain profiling tools.

The Krait L2 performance monitor counters have the capability to count the
no. of read/write transactions going out the master ports. They also have
the capability to raise interrupts when they overflow. This driver uses
those counters to determine the true usage of DDR from the Krait processor
subsystem and then recommends CPU DDR BW votes based on the measured values
and the following tunable parameters.

The driver provides various tunables that allow it to be tuned more in
favor of power or performance:

- io_percent: The percentage of the CPU time that can be spent waiting on
  memory I/O. Lower value is better performance and worse power.

- sample_ms: The sampling period in milliseconds. This only affects the
  sampling period when DDR use is ramping down or is increasing very slowly
  (See tolerance_percent).

- tolerance_percent: The minimum increase in DDR use, compared to previous
  sample, that will trigger an IRQ to immediately bump up the bandwidth
  vote. It's expressed as a percentage of the previous sampled DDR use.

- decay_rate: The parameter controls the rate at which the history is
  forgotten when ramping down. This is expressed as a percentage of history
  to be forgotten.  So 100% means ignore history, 0% mean never forget the
  historical max. The default 90% means forget 90% of history each time.

- guard_band_mbps: This is a margin that's added to the measured BW (and
  hence also the Bus BW votes) that's present to account for the time it
  takes to ramp up the DDR BW while the CPU continues to use the DDR.

- bw_step: All BW votes are rounded up to multiples of bw_step. The default
  value is 200 MB/s that turns out to ~25 or 12.5 MHz based on the SoC. A
  smaller value would mean more frequent bus BW changes. A higher value
  would mean less frequent BW vote updates, but also means at times an
  unnecessarily higher BW vote (due to the rounding up).

Change-Id: I88629a3e545cdca7160af8f8ca616ecc949d9947
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit 6cad047fc7d8cf005b9ae588c3eba30e1cfeee40)
ARM: dts: msm: Add kraitbw-l2pm device for 8974

This device provides the hardware details needed by the kraitbw_l2pm
devfreq governor to measure the DDR usage from the Krait CPU subsystem and
the IRQ that's needed to react quickly to usage changes.

Change-Id: I778a36839c9b2279ab2d912715cd7eba091fe25f
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
(cherry picked from commit c5a2aad3989bedeb995ee9c8681b1c71f04f5052)
PM: devfreq: Adapt devfreq_get_freq_level to cpubw requirements
defconfig: Enable devfreq device for CPU/BW voting
leds: leds-qpnp: Correctly terminate of_device_id array

Correctly terminate of_device_id array to avoid of_device_lookup()
incorrectly probe an additional instance of leds-qpnp device.

Change-Id: Ie6c61b4500a5fbe792e3154a761c235573c7e6bf
CRs-Fixed: 582141
Signed-off-by: Himanshu Aggarwal <haggarwa@codeaurora.org>
msm: fix incorrect termination of struct of_device_id arrays

qpnp-power-on.c didn't correctly NULL-terminate its devicetree
match table. This would result in of_dev_lookup() running off
the end of the array and looking at bogus data. Now fix this
kind of incorrect termination.

CRs-fixed: 582126
Change-Id: I44e9742af78614bd630e7d3e95dbf9f6bffc8955
Signed-off-by: Xu Kai <kaixu@codeaurora.org>
msm: kgsl: avoid zero length scatterlist allocation

During sglist allocation we calculate sglen as
per below

sglen_alloc = PAGE_ALIGN(size) >> PAGE_SHIFT;

sglen_alloc can be zero if size falls within the
last page. For example, when size = 0xFFFF_FF7B,
PAGE_ALIGN(0xFFFF_FF7B) will be 0, considering
0x1000 (4kb) PAGE_SIZE. if kzalloc() with
zero size, it will return ZERO_SIZE_PTR which is
not NULL and we always do NULL check. Dereferencing
ZERO_SIZE_PTR will lead to a distinct access fault.

Conflicts:
	drivers/gpu/msm/kgsl_sharedmem.h

Change-Id: Ibcc6198438c13b5111be0faa736328db92511597
CRs-Fixed: 563106
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
msm: pm-8x60: Register sleep status driver before regulator

During hotplug, drivers wait for core to be power collapsed to turn off
the resources used by a core in CPU_DEAD notification. The kernel
thermal module which hotplugs the core in certain conditions is
registered in the arch_initcall(). To ensure that the CPU_DEAD waits for
sleep status to be set during hotplug, register the cpu sleep status
driver before the regulator driver.

To this effect, the sleep status driver is no longer made a child device
for pm-8x60 device.

Change-Id: I772521f4b3cd18e367aa44a41d60ef9735c99ef9
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: lpm: Alter the voting mechanism for lpm drivers

Currently the power management drivers monitor the sleep votes received
for certain system wide resources such as system clock and digital voltage
rail. By knowing the sleep vote and the available sleep time , latency
requests the low power management drivers (lpm_resources module) can alter
the sleep votes for those resources during RPM notified sleep modes.

Changing this method because this method requires a new low power level be
added for each combination of the system wide resources being monitored
and that each level be characterized (latency, power etc), this method is
not very scalable as the number of system resources being monitored by the
low power management driver increases. But most of all the decisions on
whether there is enough sleep time to enter these system wide sleep modes
(residency decisions) need to be made at RPM.

This change will remove the lpm_resources module altogether and remove all
low power levels beyond those pertaining L2 cache at lpm_levels.

CRs-Fixed: 490824
Change-Id: I255b696851074dcf7bed40b648c0eb3c5c4d0d6d
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
hammerhead: Alter the voting mechanism for lpm drivers
defconfig: Disable MSM_LPM_TEST
msm: spm: add intermediate LPM mode for L2 PC

Currently when the core decide to enter into "PC + L2 PC"
LPM mode it informs to RPM and there is a chance of
system can enter into either XO or VDDmin. But this LPM
mode take longer time to enter and exit. Because of this
limitation some of the usecases where there is a less
latency APPS proc stays at lower LPM level (i.e GDFS) and
causing more power consumption. To address this issue adding
an intermediate LPM mode where L2 goes to PC but not inform
to RPM.

CRs-fixed: 552743
Change-Id: I321ff260d5baf8ac44917d67e9c9dfd260c8d5ca
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: pm: cleanup spm code related to SAW2_V1

Code related to SAW2_V1 is removed. The relevant targets
are no more built on mainline.

Change-Id: Ie3f5a9f1dab0026b02e55384b6c620db774982b1
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
msm: pm-8x60: Update the identity mapping for LPAE

The pm code uses a known stable page table with an identity mapping
for coming in and out of power collapse. This table currently assumes
a standard two level page table. This is incompatible with the new
format for LPAE. Update the code to handle both the LPAE and non-LPAE
page tables for power collapse.

Change-Id: I58097744134207fac49d7ab2147ba34f2f244a94
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
msm: mpm: Use clock API to prevent XO shutdown

When the active interrupts cannot be monitored by MPM during system
sleep modes, use linux clock APIs to vote against XO shutdown. Earlier
mpm driver relies on lpm resoures to overwrite the clock votes based on
enabled interrupts. This change decouples the MPM driver from the
lpm resources and thereby removing the dependency on RPM driver.

Change-Id: Ica5409ebb6744998303d84867f9b6d0243664b7e
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm:pm-8x60: Do not generate access flag faults for the kernel mappings

The pgd mapping (msm_pm_pc_pgd) generates Access flag fault whenever
this entry is read into the TLB for the first time. Add this flag to
the pgd mapping such that when the fault occurs, software resets the
Access flag to 1 in the translation table entry that caused the fault.
This prevents the fault from occurring the next time that memory
location is accessed.

Change-Id: I8d2ecc4d4005955ddeeaf3953ca1c445163b694c
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
msm: idle-v7: Add support to pass tz flag when core is hotplugged

When a core is hotplugged, trustzone migrates secure SPI to
the core that is online. Pass a flag to TZ indicating if it is
hotplugged or not.

Change-Id: I38d5a1987cdde9c6f3a456b7bb7726289ab0ad81
Signed-off-by: Priyanka Mathur <pmathur@codeaurora.org>
msm: pm: idle-v7 clean up

Legacy platforms are not expected to use the mainline
anymore. Unsupported targets are MSM7X01A, MSM7X25,
MSM7X27, MSM7X30, QSD8X50, MSM8X60, MSM8960,MSM8930,
APQ8064, FSM9XXX, MSM9615, MSM8625, MSM9625, MSM7X27A.

Remove unused code in idle-v7 and its related files.

Change-Id: If1fbf9eead91d3410c5c5e75cb92824b110b1138
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>