Initial commit
Init doc submodule
generic submodule
dac init
project xise file
rotor init
rs232 init
sim directory for simulation modules
Makefile with configure target

sim works only after ise synthesiz

$project -> Top; fix distclean *.xise
gitignore
simulation modules moved to sim dir renamed module cntr -> Controller removed DeboucerDebug module no longer needed
makefile
Renamed ucf
xise
simple makefile
isim cmd
Merge branch 'makefile'
maintanance whitespaces
init 0
withoug finish instruction in simulation
all wcfg
simple makefile