pwr/macros: Stop playing Russian roulette on data memory

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
clock/nva3: Parse clock control registers more accurately
clock/nva3: Set PLL refclk
clock/nva3: HOST clock
clock/nva3: Abort when PLL doesn't lock
clock/nva3: For PLL clocks always make sure the PLL is not in use
clock/nva3: Set intermediate core clock on reclocking
clock/nva3: Set some FB delay
clock/nva3: Pause the GPU before reclocking
clock/nva3: Allow user reclocking
core/device: Initialise PWR before FB

This should enable FB to do reclocking mandatory for link training from init()
clock: Add separate pre() and post() methods

To pause the engines around the entire reclocking procedure, not just for core clocks
fb/ramnva3: WIP Very special link training unit
fb/ramnva3: Use ram->base structs instead of local structs

This will ease the use of generic timing and MR generation bits later
fb/ramnva3: Ressurect timing calculation code
fb/nva3: WIP Start on some reclocking bits
fb/sddr3: WIP Expand MR generation with various bits
fb/nva3: WIP Clock up before doing ram training
pwr/memx: WIP Wait for VBLANK if desired