arm: tegra: add function to enter LP0 from cpuidle
Bug 1254633

Change-Id: I8c69d238877615a594bed6542462873f897e0ad4
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/309496
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: add config for LP0-in-idle state
Bug 1254633

Change-Id: I7130eb07f4b738db3c8fcc6a11c103741f4a72fd
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/309484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: cpu: Add interface for voltage limiting
Interface to limit the frequency as per need to limit the voltage. This
will maintain the sanity of device over extended period.

bug 1042409

Change-Id: I89ed829a8435ce34370508b9d4b21a4492826504
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/170974
(cherry picked from commit e452785cb9dfc7726168bc80eaabb9da594bb0b2)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/201610
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: Decouple edp and cpuquiet
Removed tegra_cpu_edp_favor_up/down api. EDP now requests a
PM_QOS_MAX_ONLINE_CPUS request to allow for the configuration that gives
the maximum number of MIPS given current temperature and the edp tables.

Bug 1160651

Change-Id: I2639a0f5f05901809e6249170733912b593f7549
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/333133
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>