Replaced log_assert() do { ... } while (0) hack with a static inline function
Fixed handling of invalid array access in mem2reg code
Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects
Print "SystemVerilog" in "read_verilog -sv" log messages
Some cleanups in opt_clean
Don't be too smart with $dff cells with "init" attribute on out signal