xtensa: support common clock framework

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: xtfpga: use common clock framework

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
WIP: xtensa: xtfpga: add i2c host controller to xtfpga dts

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
USB: c67x00: move URB private data allocation from under spinlock

This fixes the following warning:

  BUG: sleeping function called from invalid context at mm/slub.c:940
  in_atomic(): 1, irqs_disabled(): 1, pid: 17, name: khubd
  CPU: 0 PID: 17 Comm: khubd Not tainted 3.12.0-00004-g938dd60-dirty #1

   __might_sleep+0xbe/0xc0
   kmem_cache_alloc_trace+0x36/0x170
   c67x00_urb_enqueue+0x5c/0x254
   usb_hcd_submit_urb+0x66e/0x724
   usb_submit_urb+0x2ac/0x308
   usb_start_wait_urb+0x2c/0xb8
   usb_control_msg+0x8c/0xa8
   hub_port_init+0x191/0x718
   hub_thread+0x804/0xe14
   kthread+0x72/0x78
   ret_from_kernel_thread+0x8/0xc

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Peter Korsgaard <peter@korsgaard.com>
USB: c67x00: add proper delays to HPI read/write

According to CY7C67300 specification HPI read and write cycle duration
Tcyc must be at least 6T long, where T is 1/48MHz, which is 125ns.
Without this delay fast host processor cannot write to chip registers.
Add proper ndelay to hpi_{read,write}_reg.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Peter Korsgaard <peter@korsgaard.com>
net: ethoc: don't advertise gigabit speed on attached PHY

OpenCores 10/100 Mbps MAC does not support speeds above 100 Mbps, but does
not disable advertisement when PHY supports them. This results in
non-functioning network when the MAC is connected to a gigabit PHY connected
to a gigabit switch.

The fix is to disable gigabit speed advertisement on attached PHY
unconditionally.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
net: ethoc: set up MII management bus clock

MII management bus clock is derived from the MAC clock by dividing it by
MIIMODER register CLKDIV field value. This value may need to be set up
in case it is undefined or its default value is too high (and
communication with PHY is too slow) or too low (and communication with
PHY is impossible). The value of CLKDIV is not specified directly, but
is derived from the MAC clock for the default MII management bus frequency
of 2.5MHz. The MAC clock may be specified in the platform data, or as
either 'clock-frequency' or 'clocks' device tree attribute.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
net: ethoc: implement ethtool operations

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
net: ethoc: document OF bindings

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: xtfpga: set ethoc clock frequency

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>