Completely rewrite clocking subsystem to use Spartan 6 PLL_ADV block in order to maintain proper phasing between clocks
Undo code based on faulty assumption that the synthesized logic was fundamentally a in-->register-->combinatorial-->out structure
Add basic testbench for memory controller
Other cleanup
Increase speed of main processor to 12.5MHz
Parameterize blob extraction module
Increase official size of stack RAM to match address bus width