Sqwerty: increase EPLL to 480MHz

This is in preparation for bringing G3D on here.

Now we divide to run the audio subsystem at 96MHz.
That still allows us to divide further to produce the 19.2MHz
codec MCLK.

[endlessm/eos-shell#3348]
Mali: move clock setup to DT
Sqwerty: Move Mali to EPLL

This frees up VPLL.

It brings down the Mali clock from 533MHz to 480MHz at the same time,
but there is no performance difference in a quick es2gears test at least.

[endlessm/eos-shell#3348]
clk-exynos4: add more Exynos4412 VPLL rates

These are common VESA/CEA pixel clock frequencies.
Move FIMD to VPLL

Now we reconfigure VPLL for the exact desired pixel clock rate,
and VGA LCD compatibility now appears acceptable.