Extend SSE2 workaround beyond Athlon processors

Extends beyond Athlon processors the existing workaround here for ruby-lang's (recent?) failure to handle processors without SSE2 capabilities properly during Ruby compilation. This workaround shouldn't be limited to Athlon processors, because some Intel processors (at least), for instance Pentium III, lack Intel's Streaming Single Instruction, Multiple Data (SIMD) Extensions 2 ([SSE2](http://en.wikipedia.org/wiki/SSE2)) processor supplementary instruction set.