Kinetis clock init using #define constants

Replaced some magic constants with #defined register field values.
Introduced some MCG clock mode constants to prepare for allowing various MCG modes to be selected, e.g. FEI, FEE, PEI, etc.
Explanatory comments in kl25_clock_init
Added kl25 clock init comments from RM
Define KINETIS_SYSCLK_FREQUENCY; allow override

Use KINETIS_SYSCLK_FREQUENCY for calculations depending on the
core/system clock.  Users can override the default of
48 MHz by defining it to something else.  This frequency must be set
based on the selected MCG mode, the crystal or external clock frequency
(if applicable to MCG mode), and any FLL/PLL scaling factors;
these options are documented in hal_lld.h.
Support KL2x FEI mode

Support KINETIS_MCG_MODE_FEI, which is the default mode after reset of
the Kinetis MCU.  FLL engaged, internal 32.768 kHz reference, for an MCG
output clock of about 21 MHz.
Follow reference manual for MCG PEE mode setup

Minor change to MCG PEE mode initialization procedure based on the
Kinetis KL25 reference manual guidelines:

- Add a wait for OCSINIT0.
- Add a wait for MCG_S_PLLST.
- Move C5[PRDIV0] write to after wait on OSCINIT0, IREFST, CLKST.
Comment on low-power vs. high-gain OSC mode

Explain why the FRDM-KL25Z board should use low-power OSC mode instead
of high-gain mode, since initially no external feedback resistor is
populated.
Support Kinetis FLL (FEI/FEE) clock modes

The Kinetis MCG clock mode is selected through #defines.

Since UART0 is actually clocked from PLL/2 (PEE mode) or FLL (FEI/FEE
mode), its baud rate divisor calculation needed to be able to take into
account the correct input clock frequency. For UART1 and UART2, the
bus/flash clock is used.
Merge pull request #6 from cdbennett/clock_init

Enhanced Kinetis clock initialization