Caches: Rename index->tag

The index points to the offset in the cache and tag memory. The tag is
the part left of the index in the address and it is stored in the tag
memory at the addressed index, not the index is stored in the tag.

Some beautification and documentation
Caches: Optimized LRU unit

This is the generic LRU unit. It uses an optimized vector which is of
size (NUMWAYS*(NUMWAYS-1))>>1. The content of the vector is the
reduced set of direct comparisons (x<y) where x is older than y. As
the module forbids x is equally old as y we have a symmetric behaviour
(x<y)=!(y<x).

For four ways the vector is then:

history [5:0] = {(2<3),(1<3),(1<2),(0<3),(0<2),(0<1)}

Further details, the instantiation and the algorithm itself are
documented in the module.
Caches: Support multiple ways

Adds support for more than two ways. The memories are accordingly
replicated, the status vector extended, and some extra multiplexing
added. The caches still use LRU and utilize the optimized LRU unit.
dcache: save copy of tag data on refill

The data read from the tag memory might be change during a refill,
so it's necessary to keep a copy around until the data is written back.

9e5a414 Caches: Support multiple ways
removed the old tag saving code, and correctly replaced it in the icache,
but the respective change was omitted from the dcache changes.
dcache: invalidate from READ state

If an invalidate request would occur while in READ state,
the request would be indefinitely ignored.
This adds a state change to the IDLE state on the invalidate signal,
which will assert the correct address and continue to the INVALIDATE state.
cache: use per-block unique for-loop index variables

Icarus can't handle several different blocks that are using the
same for-loop index variable.
cappuccino/ctrl: set npc to pc_ctrl_i on trap stall

A stall caused by a trap instruction (sw breakpoint) should set
npc to the pc where the stall ocurred. Since the exception
signal goes high in ctrl/mem stage, the current pc is pc_ctrl_i.
cappuccino: add support to read gpr via spr

This adds an extra register file read port, for access to the
gpra via spr.
So far only read access.
The motivation for adding a complete seperate rf_ram is that
it's least intrusive and muxing the address port of one of
the 'real' rf_rams can be avoided.
The downside is of course that it's a bit of a resource waste.
add support for l.lwa/l.swa atomic instructions

This adds support for the l.lwa and l.swa atomic instructions
per the suggestion here:
https://www.dropbox.com/s/yqyfelu2yrutzwt/openrisc-arch-1.1-rev0.pdf

Currently only cappuccino makes use of them
cappuccino/fetch: deassert ibus_req on rst