xtensa: xtfpga: set up MII management bus frequency

Without this setup OpenCores MAC can read PHY registers on KC705 running
at 50MHz, but cannot write there. Initial CLKDIV value appears to be 2,
making MII management bus run at 25MHz, while Marvell 88E1111 PHY
requires minimum 120ns MDC cycle, which is ~8.3MHz.

Request 2MHz MDC frequency to make even slower PHYs from older boards
work.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>