In intr_event_handle() we already save and set td_intr_frame, so
don't do it also in ia64_handle_intr(). With ia64_handle_intr()
not saving and setting td_intr_frame, make sure to do it for
clock interrupts in ia64_ih_clock().
Add more obsolete files
Use the same terminology as the ARM docs in comments. No functional changes.
Use armv7 TLB flush code, not arm11, for cortex-a processors.

The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware.  That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation.  On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.