F4 basically done

This commit leaves the F4 rcc.c with the top layer API intact and the most
common #defines for clock setups with the PLL. It does not remove the former
clock setting functions.
F0 RCC brought up to spec

Updated the F0 rcc code to bring it into alignment with the cleaner
path. Once done it should be possible for any STM chip to use
rcc_pll_clock_setup(RCC_xMHZ_HSI_maxMHZ_PLL, RCC_HSI_FREQUENCY); to set
the clock to the maximum clock frequency for that chip using the HSI
clock.