Initial work on a very incomplete serial 'memory monitor'

Currently, the only 'memory' it accesses is a fake one, which returns
(address[7..0] xor address[15..8]) as data byte. Only reading is
implemented now, but I may add writing later. The ultimate goal is
to be able to use it to debug the upcoming SPI and SDRAM code.
Merge branch 'master' of /home/kfoltman/fpga-check/../fpga