cappuccino/wb_mux: remove unused lsu_valid_i input
execute_alu: remove & {OPTION_OPERAND_WIDTH{1'b1}} from mul

Several synthesis tools seems to be confused by the intention of this,
there have been reports about problems with Synplify and
ISE seem to add redundant logic.
execute_alu: Set result of disabled units to 0

Apart from being more sensible, it seems some tools can make
better optimization decisions from signals tied to 0.
dcache: minor whitespace fix
dcache: disable bypass for tag ram

There's always a one cycle 'reload' time accounted for in the
FSM, so using a write-on-read bypass is not necessary.
We still have to keep the bypass on the data ram,
since that is used when doing multiple byte-selected writes
to a single word in a row.
mor1kx_execute_alu: logic operation optimizations

Use a look-up-table instead of separately calculate and/or/xor.
execute_alu: tidy up logic optimization

The optimizations in bba8660
('mor1kx_execute_alu: logic operation optimizations'),
was provided as a proof-of-concept by Florent.
I however decided to pick that as is and do the tidy up in this
seperate commit.
This sprinkles some comments around, fixes a couple of coding
style issues and tries to make it a bit easier to read.
Merge branch 'upstream/master' into 'origin/withfpu'