sandybridge: Allow skipping mrc.cache

On X230 MRC fails if cache is passed to it. Until better solution is found
do not create mrc.cache

Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash

CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
CBMEM intel: Define get_top_of_ram() once per chipset

Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.

Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.

Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
google/stout: Add EARLY_CBMEM_INIT

Required for MRC cache and for HAVE_ACPI_RESUME to work.

Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4665
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Intel (sandy/ivy): Avoid calling cbmem_initialize() twice

Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.

Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
ROMSIZE: Add option for 12M chips.

On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.

Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4688
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable `Start_vid`

When adding support for PSS object generation for AMD pre Family Fh CPUs
(199c694f) the function `pstates_algorithm` was copied and adapted, but
`Start_vid` is not needed anymore as a static table is used. I’d remove
the variable, but Ron Minnich requested to leave it there for
documentation purposes. So just comment it out.

Change-Id: I3002951d168cade6461941c16d78373c47792e13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4036
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
AMD Hudson: show POST codes on a PCI device

Show POST codes on a PCI device: implement hudson_pci_port80().
Remove the comments that use pci_locate_device():
using the code found in the comment seems to break booting.

This shares much code with sb600/sb700/sb800,
however the deduplication work needs to be discusses somewhere else
than in this review board.

Tested on an Asus F2A85-M.
The contribution is (C) by Rudolf Marek.

Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
Author: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4559
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
butterfly: fix compilation with !CHROMEOS

One of arguments to cbfs_get_file_content was missing.

Change-Id: Icb4ef26f18d63c133bc32f1c62a524edee0621ea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4696
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
cpu/intel: Make all Intel CPUs load microcode from CBFS

The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
cpu/intel: Remove dummy terminators from microcode blobs

Now that CBFS microcode no longer requires a NULL termination, remove the
dummy terminators from all microcode blobs. This also enables microcode
blobs from different CPU models to be linked in the same
cpu_microcode_blob.bin without the terminators getting in the way.

Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4506
Tested-by: build bot (Jenkins)
cpu/allwinner/a10: Add minimal ramstage driver

Change-Id: I857755976b17b0e492c086162f395a77933eeed8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[RFC] drivers: Import generic MMC handler from uboot

Aye and behold, the wonderful world of MMC and SD cards.
This is the MMC handler imported from uboot and adjusted for coreboot
use. There are over 100 micro-commits to refactor and clean up the
ubootian style, so there is no sense in saying what uboot revision
this came from (yeah, Paul, I'm looking at you).

Let's be honest. This code is a clusterfuck in a coreboot-flavored
candy coating. There's probably so much more work to do, that I didn't
bother cleaning up the comments. I need a general direction on this.
How do we even start bringing this up to coreboot standards? We'll
need this for the Allwinner ports.

There's also the SoC specific MMC driver, but that one is not included
here. I want to get a perspective from someone who's never had to
endure the pains of uboot code.

Change-Id: Ied5ac5701d2fe8338fd92477110d6f74a4295371
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
NFM cpu: Import sunxi MMC driver from uboot

Change-Id: I8417875737a5f8e1dc21325ad5d6d245423f68cb
NFM cpu: Add clock reg definitions for SD clock

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
cubieboard: add basic SD init and testing

Change-Id: I63302b87b583ed62794559238b8b1ae19aba3f81
NFM cpu: use SD card for bootblock media

Change-Id: Ie0b123023c53e485c41650c1fc7b0fb69a286a30
CPU: bootblock_media, cache entire rom to RAM

Change-Id: I6ec78ae2b173d054a80584315bd2698c618f5b89
bootblock: use ramsegs

Change-Id: Icbb3b1726ff649a8f08a0b5d86c5138f3e21cb96