gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()

IDMAC channels can have a burtsize of 20 pixels, so allow for that in
ipu_dmfc_setup_channel().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Remove ipu_dmfc_init_channel()

The function ipu_dmfc_init_channel() sets the "WAIT4EOT" mode according
to the line width and the DMFC channel's FIFO size (the slots parameter).
But this can only happen after slots has been calculated in
ipu_dmfc_alloc_bandwidth().

Fix by renaming ipu_dmfc_init_channel() to a static dmfc_set_wait_eot()
which is called at the end of ipu_dmfc_alloc_bandwidth(), after slots
has been calculated.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()

The dmfc mutex was being acquired in ipu_dmfc_free_bandwidth(), freed,
then immediately re-acquired in ipu_dmfc_alloc_bandwidth(). Acquire
the lock once at the beginning of ipu_dmfc_alloc_bandwidth().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Enumerate the DC channel names

Define the names of the DC channels, and reference them in ipu-dc.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-di: Move ipu pointer init

Move the init of di->ipu pointer to near top of ipu_di_init().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-di: Add and improve debug/error messages

Add a couple error messages to ipu_di_init() for better IPU
load/unload debug. Add more debug messages.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg

This patch changes signal names in struct ipu_di_signal_cfg
as per the industry standard names, and renames fields that
were using CamelCase.

Signed-off-by: Deepak Das <deepak_das@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-di: Set rate of DI pre clock

This patch sets the rate of the DI pre clock to support a much wider
range of pixel clock frequencies.

It does this by calculating two values for the pre-clk rate: a
rate that is a whole integer multiple of the pixel clock, and a rate
that is a half-integer multiple. It then programs whichever rate
comes closest to generating the desired pixel clock, and uses the
corresponding integer or half-integer divider.

The reason only whole or half integer DI dividers are used is because
of a chip bug in the fractional part of DI Base Sync Clock Gen 0 register
(see discussion in FSL community site at
https://community.freescale.com/thread/308577).

Quoting from that thread:

"Pixel IPU clock for Display has high jitter and does not have 50% duty cycle.
This is expected behavior, when the clock divider is set to a value that is not
an integer. When the divider is set to a non-integer value, the average
frequency of the clock will be correct, but the clock will jitter."

According to our experimentation, only 0x8 for the fractional part seems
to generate clock waveforms that are tolerated by most displays (this
hasn't been proved officially).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
gpu: ipu-v3: Add RGB666 interface pixel map

Adds RGB666 to the pre-loaded interface pixel maps.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*

Pass a drm pixel format fourcc to ipu_cpmem_set_yuv_interleaved(),
ipu_cpmem_set_yuv_planar_full(), and ipu_cpmem_set_yuv_planar(),
instead of a v4l2 pixel format. The remaining cpmem API that still
accepts a v4l2 format is now only ipu_cpmem_set_image(), since this
function is called by v4l2 drivers.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()

Adds ipu_drm_fourcc_is_planar(), which is equivalent to
ipu_pixelformat_is_planar() but accepts a drm fourcc format.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add IDMA channel linking support

Adds functions to link and unlink IDMAC source channels to sink
channels.

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -> IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM      -> IPUV3_CHANNEL_MEM_ROT_PP

More links can be added to the idmac_link_info[] array.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-cpmem: Support YVU422

Add simple hooks to support YVU422 in cpmem.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()

Adds ipu_cpmem_get_burstsize().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>