i965/fs: Fix Broadwell texture header setup to be uncompressed.

MOV_RAW disables masking, but doesn't force the instruction to be
uncompressed.  That needs to be done by hand.

Fixes textureGather and texture offset tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Support arbitrarily large sampler indices on Broadwell+.

I added support for these on Haswell, but forgot to update the Broadwell
code before landing it.  Partially fixes Piglit's max-samplers test.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/vec4: Support arbitrarily large sampler indices on Broadwell+.

I added support for these on Haswell, but forgot to update the Broadwell
code before landing it.  Fixes Piglit's max-samplers test.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Implement a CS stall workaround

According to the latest documentation, any PIPE_CONTROL with the
"Command Streamer Stall" bit set must also have another bit set,
with five different options:

   - Render Target Cache Flush
   - Depth Cache Flush
   - Stall at Pixel Scoreboard
   - Post-Sync Operation
   - Depth Stall

I chose "Stall at Pixel Scoreboard" since we've used it effectively
in the past, but the choice is fairly arbitrary.

Implementing this in the PIPE_CONTROL emit helpers ensures that the
workaround will always take effect when it ought to.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Also emit VF_INSTANCING in the no-elements case.

I can't imagine why this would matter since there's no actual data being
pulled, but...for safety?

Not observed to help anything
i965/gs: Fix EndPrimitive on Broadwell.

My earlier patch (i965: Reserve space for "Vertex Count" in GS outputs.)
incremented Global Offset for most URB writes to make room for the new
"Vertex Count" field, but failed to shift the URB writes used for
writing control bits.

Confusingly, Global Offset must be incremented by 2 here, rather than 1.
The URB writes we use for actual data are HWord writes, which treat
Global Offset as a 256-bit offset.  These are OWord writes, so it's
treated as a 128-bit offset instead.

Cc: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add missing sample shading bits to Gen8's 3DSTATE_PS_EXTRA.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Enable Broadwell support.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Use MOV, not OR for setting URB write channel enables on Gen8+.

On Broadwell, g0.5 contains the "Scratch Space Pointer"; using OR
puts some bits of that into "ignored" sections of our message header.

While this doesn't hurt, it's also not terribly /useful/.  Using MOV
is sufficient to set the only interesting bits in this part of the
message header.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Drop VECTOR_MASK_ENABLE in Broadwell's 3DSTATE_VS packet.

We never set it on previous generations, but I had to set it in
3DSTATE_PS for correct behavior.  For symmetry, I set it in 3DSTATE_VS
as well, but there's no actual need to do so.  Piglit works fine either
way.  The documentation also remarks that there should never be a need
to program this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Fix General and Indirect Base Addresses on Broadwell.

I set the "address modify enable" bit in the wrong DWord.  The first
DWord is the high 16 bits of the address, while the second is the low
32-bits and enable bit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
stash - vp fixes?

doesn't seem to actually fix anything.

oh, this might only be relevant when I turn on the viewport extents test
i965: Drop bogus F32TO16/F16TO32 instructions on Broadwell - use MOV.

Broadwell removed the F32TO16 and F16TO32 instructions.  However, it has
actual support for HF values, so they're actually just MOV.

Fixes vs-packHalf2x16 and vs-unpackHalf2x16 tests (both the ARB
extension and ES 3.0 variants).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Implement FS_OPCODE_[UN]PACK_HALF_2x16_SPLIT[_XY] opcodes.

I'd neglected to port these to Broadwell.  Most of this code is copy
and pasted from Gen7, but instead of using F32TO16/F16TO32, we just
use MOV with HF register types.

Fixes fs-packHalf2x16 and fs-unpackHalf2x16 tests (both the ARB
extension and ES 3.0 variants).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Store absolute thread count in max_wm_threads on Broadwell.

In the past, 3DSTATE_PS took an absolute number of threads.  Conversely,
on Broadwell you always program 64, and it implicitly scales based on
the GT-level with no special programming.  So, I stored 64 in
brw_device_info::max_wm_threads.

However, I didn't realize that we also use max_wm_threads to compute the
size of the scratch space buffer.  In that case, we really need the
absolute number of threads.

This patch hardcodes 3DSTATE_PS to use the value it expects, and changes
max_wm_threads back to a (completely fake) absolute thread count (once
again copied from Haswell).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add Gen8 assembly support for DP Scratch messages.

The new accessors will make it easy to do Gen7-style scratch messages.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965/fs: Implement scratch read/write support for Broadwell.

To make sure that both the Gen4 and Gen7 style messages work, I
initially disabled the SHADER_OPCODE_GEN7_SCRATCH_READ optimization,
ran Piglit, re-enabled it, and ran Piglit again.  Both worked fine.

Fixes 40 Piglit tests (most of the varying-packing category).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Pull format conversion logic out of brw_depthbuffer_format.

brw_depthbuffer_format is not very reusable at the moment, since it
uses global state (ctx->DrawBuffer) to access a particular depth buffer.

For HiZ on Broadwell, I need a function which simply converts the
formats.  However, at least one existing user of brw_depthbuffer_format
really wants the existing interface.  So, I've created a new function.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Program 3DSTATE_HIER_DEPTH_BUFFER properly on Broadwell.

HiZ buffers still don't exist, but when they do, we'll set them up.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Bump generation check in code to disable HiZ at LODs > 0.

Broadwell's "HiZ Resolve" operation still has the restriction that the
rectangle primitive must be 8x4 aligned.  So I believe we still need
this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>