[TASK] Remove synchronizers for readdata path in prlMaster

The readdata is held by the bus slave with the ack signal. Therefore the
readdata bus is surely stable when the bus master reads it.

Change-Id: I1b3188d09e3ad3091a6c3a04e00fae9c03d2e961
[FEATURE] Add SDC timing constraints for parallel interface ipcores

Add SDC timing files for parallel interface ipcores, which are configured by
Qsys instantiation.

Change-Id: I0294bd0dbbe7ae19ac5e3441039d38d79f18ef88
[FIX] Fix parallel slave ALE input

- Uncouple ALE from CS (shortens combinational input path)
- Capture address latch output together with byteenable (relax timing)

Change-Id: I8e41c8229468b43cc8d4793941d30cb19d0ef8bd