Bus routing by hand.
Correct wire handling on data bus gate read and write connectors.
Added clr input to registers
Created bitregister but not designed or implemented yet
Designed bitregister but implementation is not finished yet.
Added setBit and getBit and testing it.
Setting wires correctly to active.
Improved bitregister and fixed bug in Bus.
Consider State for writing wires.
Updating wires on bus read or write.
Wider AND-gate and better wire positions.
Bonsai component setup
Better memory connection positions.
Bonsai component setup
Merge branch 'develop' of github.com:KlausMerkert/Bonsai into develop
Clickable bits in the BitRegister
Merge remote-tracking branch 'origin/develop' into develop
Bus was too small.
Delay finished.
Filter component created. Still work to do.