ENGR00298393 pcie: rc can access mem of ep

- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
- change the test region size to be 15MB.

NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/platform/imx-pcie/ep_bar0_addr

1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  EFE9EDF4 7583FB39 39EAFFEA FBDCFD78

step2:
RC side:
memtool -32 0x01000000=58D454DA
memtool -32 0x01000004=7332095B

step3:
EP side:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  58D454DA 7332095B 39EAFFEA FBDCFD78

Signed-off-by: Richard Zhu <r65037@freescale.com>
ENGR00298394 pcie: enable imx pcie ep msi demo

- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system

Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images

- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #

- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496:          1          0          0          0  PCIe-MSI

- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000

- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
496:          2          0          0          0  PCIe-MSI

Signed-off-by: Richard Zhu <r65037@freescale.com>
Add Xillybus driver to driver/char/ in a separate directory

For more information about Xillybus, see http://xillybus.com

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Xillybus driver added to Kconfig and Makefile in drivers/char/

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
ENGR00300417: [MX6SL] Add 100M and 24M MMDC parameters for MX6SL LPDDR2

Use different MMDC parameters for 100M and 24M of i.MX6SL LPDDR2

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00267929: [MX6SL] Add DDR3 support for MX6SL

Add DDR3 support for MX6SL

Signed-off-by: Grace Si <b18730@freescale.com>
ENGR00306276: iMX6: Add workaround for ARM errata 761320 and 794072

These are Category B, hence workaround is essential.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
ENGR00306992 Update the code to rel_imx_3.10.17_1.0.0_ga release

Code is sync to
232293e0abb46639e188ab9d8643f1dbf94534f6

* ENGR00306992 Revert "ENGR00302036-3 [#1078]gpu2d may cause bus hang in
* some corner case"

Date: May 09,2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00306397 [#1118] use BUG_ON to check if GPU clock is off

Access GPU register will cause system hang(bus lock-up) without log when clock is off,
GPU kernel BUG_ON is added to check if GPU clock is off when read & write GPU registers,

GPU clock issue can be easily identified with the detailed kernel panic log as below:

kernel BUG at drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c:2423!
Unable to handle kernel NULL pointer dereference at virtual address 0000000
...
[<c0050008>] (__bug+0x1c/0x28) from [<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc)
[<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc) from [<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc)
[<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc) from [<c0475e0c>] (_TryToIdleGPU+0x70/0x12c)

Mutex protection is not necessary for interrupt handling, because GPU clock is only turned off
by interrupt worker thread during clock gating.

Date: Apr 11, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 50c3767eb19bb22f395215755dac220f4bbb2f14)
ENGR00308233-2 [#791]Refine wclip workaround algorithm 001

Vivante patch name:0001-more-refinements-for-wclip-issue

Date: Apr 14, 2014

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00308233-3 [#791]Refine wclip workaround algorithm 002

Vivante patch name:0002-more-refinements-for-wclip-issue

Date: Apr 14, 2014

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00308233-4 [#791]Refine wclip workaround algorithm 003

Vivante patch name:000e-more-refinements-for-wclip-issue

Date: Apr 14, 2014

Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00310166 [#1157] disable GPU recovery function

Disable GPU auto recovery so that GPU can dump the stack.
GPU support auto recovery function, when GPU meet some issue
it will try to do recovery, but most of cases GPU can't really
recovery, we do find some cases GPU can recovery for example
some 2D hang, but customer is not accept such recovery, so show
the GPU stack dump and find the root cause is the correct way.

Date: Apr 24, 2014

Signed-off-by: Richard Liu <r66033@freescale.com>
(cherry picked from commit 888c79ab0f114b7b259266fc82c1399cbb926faf)
ENGR00309915 [#1087] enhanced video memory mutex

this patch can fix NULL pointer issue in GPU kernel driver with the following log

[<7f240438>] (gckEVENT_AddList+0x0/0x810 [galcore]) from [<7f239ebc>] (gckCOMMAND_Commit+0xf28/0x118c [galcore])
[<7f238f94>] (gckCOMMAND_Commit+0x0/0x118c [galcore]) from [<7f2362dc>] (gckKERNEL_Dispatch+0x120c/0x24e4 [galcore])
[<7f2350d0>] (gckKERNEL_Dispatch+0x0/0x24e4 [galcore]) from [<7f222280>] (drv_ioctl+0x390/0x540 [galcore])
[<7f221ef0>] (drv_ioctl+0x0/0x540 [galcore]) from [<800facd0>] (vfs_ioctl+0x30/0x44)

The false code is at 0x217bc where the 0-pointer happens (r3 = 0)

gcuVIDMEM_NODE_PTR node = (gcuVIDMEM_NODE_PTR)(gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node));
   217b8:                e5953028             ldr           r3, [r5, #40]         ; 0x28

                if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
   217bc:                e5932000             ldr           r2, [r3]
   217c0:                e5922000             ldr           r2, [r2]
   217c4:                e152000a             cmp       r2, sl
                {
                     gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,

Date: Apr 23, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit fcde214d8c793d4dd785e47175b5833f1f3f5f1f)
ENGR00308899 [#1087] enhanced GPU database protection

the potential risk is found in special case when application exit,
deleting record will cause the unexpected issue when process database is destoryed without atom protection

the enhanced database patch should be applied to avoid the unexpected kernel issue

Date: Apr 17, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit e799c1ae023264c0e1e1e41d448e30e2304944e1)
ENGR00306992-2 gpu:gpu2d may cause bus hang in some corner case

Vivante patch name:
fix_fsl_2d_base_on_p13.v2.rls.diff

-Updated the outstanding request limit to 12.
-Refined the 2D chip feature check.
-Refine the 2D cache flush operation
(avoid FE and PE access memory through the same port).
-Enable cache flush for filterblt.
-Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
-Use brush stretch blt for clear operation.
-Enable SplitFilterBlit to workaround the 2d hang issue in filterblit case.
-Refine 2d line operation.

Date: May 05, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
ENGR00312477 [#1162] fixed gpu lower memory killer

mutex operation is performed in gckKERNEL_QueryProcessDB
remove spinlock for gckKERNEL_QueryProcessDB to avoid scheduling issue

Date: May 08, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 554581201c0a1c2c7caddad5750b1fd678e09c8c)
ENGR00314119 [#1183] fixed database mutex multi-lock issue

The abnormal flow with the monkey test freeze problem is as below:
gckKERNEL_DestroyProcessDB--> aquire mutex --> gckCOMMAND_Detach(gckEVENT_FreeContiguousMemory) -->
___RemoveRecordFromProcessDB --> gckKERNEL_RemoveProcessDB --> aquire the same mutex

the fix is to disable mutex lock when perform record destory operations

Date: May 19, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 8d62ea9a655f1bb0ca86af222de7625abc8d2bc8)
ENGR00316182: [imx6x] Fix bugs in clock and cpufreq code.

Cpufreq code:
1. Busfreq can be dropped to 24MH only when CPU freq is at the lowest setpoint (396MHz). The
code was incorrectly releasing the request for high busfreq even when cpufreq was at 792MHz.
This caused incorrect pll2 behavior as the busfreq code expects CPUFREQ to be at 396MHz and
to be sourced from PLL2_PFD2_396M when the switch to low_bus_freq is requested.

Clock code:
1. Ensure osc_clk usecount is also updated when pll2 or pll1 usecount is changed.
This fixes a debug warning message when CLK_DEBUG is enabled.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
ENGR00316180: [iMX6x] Support IRAM page table when DDR is in self-refresh.

Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
   This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
   This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.

The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.

This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
   This makes it possible to create entries for the IRAM code in the
   IRAM page table. We need to ensure that both the DDR and IRAM page
   table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
    a. TTBCR.N = 1
     This means the 0-2G virtual address space is translated using TTBR0
     and 2G-4G is translated using TTBR1.
    b. Set TTBCR.PD0 = 1
      With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1

Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible. Only the WFI and suspend code that puts DDR into self-refresh
is located in this 8k. The DDR frequency code that also puts the DDR into
self-refresh need not be located in this 8K region. Currently this patch
allocates a separate 4K region in IRAM for the DDR frequency change code.

Additional conditions to be met:
1. Disable L2 when DDR is in self-refresh.
2. Ensure that L1 and branch prediction are disabled when we
are switching to IRAM page tables, based on recommendation from
ARM.

This patch also dynamically calculate size of all the code that puts
DDR into self-refresh (low power and ddr freq change).

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>