shorten the demo file name
change reg_32

avoid spike
upload
sync datapath
Merge branch 'master' of https://github.com/sidjos/Single_Cycle_Datapath
adding library
working
test file
zero=>equal0
modify branch
add two signals from the alu control  logic

add beq_branch, bne_branch
Merge branch 'master' of https://github.com/sidjos/Single_Cycle_Datapath
Merge branch 'master' of https://github.com/sidjos/Single_Cycle_Datapath
sync
New register memory
Sync
good version of files, new memories
works with init