OMAP4 NAND updates (squash)
found @ bsmitty's repo @ https://github.com/bsmitty83/DirtyV_tuna

 OMAP4: NAND: Fix occasional errors and improve performance

The NAND command functions were not waiting for the attached chip to
indicate ready for some functions that they should have.  The changes
here reflect the use of the ready line by the Micron MT29F NAND Flash
Memory datasheet.

The routine omap_dev_ready() used the WAIT0EDGEDETECTION bit in the
GPMC_IRQSTATUS register.  This bit changes well after the NAND chip
raises the GPMC_WAIT0 input to indicate that it is ready.  The result
is that NAND reads and writes are quite slow.  It takes longer for
WAIT0EDGEDETECTION to reflect the proper status than it does to read
a page of data out of the NAND chip following the read command.  The
driver now uses WAIT0STATUS in the GPMC_STATUS register as per the TRM.

Signed-off-by: Steve Schefter <steve@scheftech.com>

OMAP: NAND BCH: Add eccsize and eccbytes to bcn struct

In the BCH4/8 support for OMAP2 is done only partly in hardware.
The error correction itself is done in software.
To use the lib/bch for error correction some changes have to be in the nand_bch.
The omap uses for bch8 eccsize=2048 and eccbytes=52 but does the
actual check and correction in four sub blocks. So we use in the nand_bch
code the eccsize=512 and eccbytes=13.
The used eccsize/eccbytes have to be saved in the bcn struct.

Signed-off-by: Steve Schefter <steve@scheftech.com>

OMAP4: NAND: use dev ready

Enable the use of the dev ready (GPMC_WAIT0) signal from the NAND
chip.  This increases the performance of NAND access.

This commit also modifies omap_write_buf_pref() to improve
performance and fixes DMA support for NAND.  The latter is not
turned on as it has a negative impact on NAND speed.

Signed-off-by: Steve Schefter <steve@scheftech.com>

Conflicts:
	drivers/mtd/nand/omap2.c

 NAND: timing requirements not met

After the driver issues the commands NAND_CMD_SEQIN and
NAND_CMD_STATUS the chip does not assert the wait line, but it is
not immediately ready.  The driver must wait tADL and tWHR
respectively.

Signed-off-by: Steve Schefter <steve@scheftech.com>

OMAP4: NAND: fix for read error

Because the NAND interface uses the OMAP's general purpose memory
controller, part of the interface is implemented in software.
Specifically, the NAND driver monitors the ready line from the NAND
chip.  This is done using the WAIT0STATUS bit in the GPMC_STATUS
register.  It has been found that this can, on rare occasions for
at the start of a page read, indicate ready when the device is not
really ready to present the data.  Two positive reads produce
reliable results.  See details in omap_dev_ready().

While investigating this change, it was noted that the timing
specs for the NAND chip require a delay of tRR after the chip
indicates ready before it is actually ready to provide the data.
This was implenented in nand_command() and nand_command_lp(),
although no problem was observed without this delay.

Testing indicates that these changes have little or no effect
on the NAND read and write speeds.

Signed-off-by: Steve Schefter <steve@scheftech.com>
android/lowmemorykiller: Wait for memory to be freed

The memory reclaim code needs to give time to the system to
return the memory from a killed process otherwise the memory
reclaim code could run continuously, in multiple threads,
which could starve both the watchdog thread and the thread
which is responsible for returning the memory from the
killed process.

Change-Id: Ieded4bfe038ca936247fa4b638070e979b02eaa1
CRs-fixed: 447740
Signed-off-by: Liam Mark <lmark@codeaurora.org>

Conflicts:
	drivers/staging/android/lowmemorykiller.c
ARM: support XZ compressed kernels

Wire up support for the XZ decompressor

Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
Increase the maximum temperature treshold.

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
Revert "android/lowmemorykiller: Wait for memory to be freed"

This reverts commit d8cf625571bff4b84eca758fd2ead77b6ec284ce.
panel-s6e8aa0.c: add contrast module. Original implementation from morfic

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
[PATCH] lib: Improve the performance of string.c

The performance of memcpy and memmove of the general version is
very inefficient, this patch improves them.

Taken from Arne Coucheron
Added Battery Life eXtender (BLX) version 1. - From Ezekeel
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>

Conflicts:

	drivers/misc/Kconfig
	drivers/misc/Makefile

Conflicts:
	drivers/misc/Makefile
Added Color Control version 4.

Conflicts:

	drivers/misc/Kconfig
	drivers/misc/Makefile
    drivers/video/omap2/displays/panel-s6e8aa0.c

Conflicts:
	drivers/misc/Makefile
	drivers/video/omap2/displays/panel-s6e8aa0.c
Add memcopy.h
lib/sha1: use the git implementation of SHA-1

For ChromiumOS, we use SHA-1 to verify the integrity of the root
filesystem.  The speed of the kernel sha-1 implementation has a major
impact on our boot performance.

To improve boot performance, we investigated using the heavily optimized
sha-1 implementation used in git.  With the git sha-1 implementation, we
see a 11.7% improvement in boot time.

10 reboots, remove slowest/fastest.

Before:

  Mean: 6.58 seconds Stdev: 0.14

After (with git sha-1, this patch):

  Mean: 5.89 seconds Stdev: 0.07

The other cool thing about the git SHA-1 implementation is that it only
needs 64 bytes of stack for the workspace while the original kernel
implementation needed 320 bytes.

Signed-off-by: Mandeep Singh Baines <msb@chromium.org>
Cc: Ramsay Jones <ramsay@ramsay1.demon.co.uk>
Cc: Nicolas Pitre <nico@cam.org>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: linux-crypto@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Remove ARM SHA1 routines

Since commit c6cdf9c ("lib/sha1: use the git implementation of
SHA-1"), the ARM SHA1 routines no longer work.  The reason? They
depended on the larger 320-byte workspace, and now the sha1 workspace is
just 16 words (64 bytes).  So the assembly version would overwrite the
stack randomly.

The optimized asm version is also probably slower than the new improved
C version, so there's no reason to keep it around.  At least that was
the case in git, where what appears to be the same assembly language
version was removed two years ago because the optimized C BLK_SHA1 code
was faster.

Reported-and-tested-by: Joachim Eastwood <manabian@gmail.com>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Remove sha1.S

arm: remove stale export of 'sha_transform'

The generic library code already exports the generic function, this was
left-over from the ARM-specific version that just got removed.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>